2 * (C) Copyright 2007-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <asm/ppc4xx-gpio.h>
29 /* Only compile this file for boards with GPIO support */
30 #if defined(GPIO0_BASE)
32 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
33 gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
36 #if defined(GPIO0_OSRL)
37 /* Only some 4xx variants support alternate funtions on the GPIO's */
38 void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
47 if (pin >= GPIO_MAX) {
52 if (pin >= GPIO_MAX/2) {
54 pin2 = (pin - GPIO_MAX/2) << 1;
57 mask = 0x80000000 >> pin;
58 mask2 = 0xc0000000 >> pin2;
60 /* first set TCR to 0 */
61 out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
63 if (in_out == GPIO_OUT) {
64 val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
67 val |= GPIO_ALT1_SEL >> pin2;
70 val |= GPIO_ALT2_SEL >> pin2;
73 val |= GPIO_ALT3_SEL >> pin2;
76 out_be32((void *)GPIO0_OSRL + offs + offs2, val);
78 /* setup requested output value */
79 if (out_val == GPIO_OUT_0)
80 out_be32((void *)GPIO0_OR + offs,
81 in_be32((void *)GPIO0_OR + offs) & ~mask);
82 else if (out_val == GPIO_OUT_1)
83 out_be32((void *)GPIO0_OR + offs,
84 in_be32((void *)GPIO0_OR + offs) | mask);
86 /* now configure TCR to drive output if selected */
87 out_be32((void *)GPIO0_TCR + offs,
88 in_be32((void *)GPIO0_TCR + offs) | mask);
90 val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
91 val |= GPIO_IN_SEL >> pin2;
92 out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
95 #endif /* GPIO_OSRL */
97 void gpio_write_bit(int pin, int val)
101 if (pin >= GPIO_MAX) {
107 out_be32((void *)GPIO0_OR + offs,
108 in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
110 out_be32((void *)GPIO0_OR + offs,
111 in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
114 int gpio_read_out_bit(int pin)
118 if (pin >= GPIO_MAX) {
123 return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
126 int gpio_read_in_bit(int pin)
130 if (pin >= GPIO_MAX) {
135 return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
138 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
139 void gpio_set_chip_configuration(void)
141 unsigned char i=0, j=0, offs=0, gpio_core;
142 unsigned long reg, core_add;
144 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
147 /* GPIO config of the GPIOs 0 to 31 */
148 for (i=0; i<GPIO_MAX; i++, j++) {
149 if (i == GPIO_MAX/2) {
154 core_add = gpio_tab[gpio_core][i].add;
156 if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
157 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
159 switch (gpio_tab[gpio_core][i].alt_nb) {
164 reg = in_be32((void *)GPIO_IS1(core_add+offs))
165 & ~(GPIO_MASK >> (j*2));
166 reg = reg | (GPIO_IN_SEL >> (j*2));
167 out_be32((void *)GPIO_IS1(core_add+offs), reg);
171 reg = in_be32((void *)GPIO_IS2(core_add+offs))
172 & ~(GPIO_MASK >> (j*2));
173 reg = reg | (GPIO_IN_SEL >> (j*2));
174 out_be32((void *)GPIO_IS2(core_add+offs), reg);
178 reg = in_be32((void *)GPIO_IS3(core_add+offs))
179 & ~(GPIO_MASK >> (j*2));
180 reg = reg | (GPIO_IN_SEL >> (j*2));
181 out_be32((void *)GPIO_IS3(core_add+offs), reg);
186 if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
187 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
189 u32 gpio_alt_sel = 0;
191 switch (gpio_tab[gpio_core][i].alt_nb) {
197 * else -> don't touch
199 reg = in_be32((void *)GPIO_OR(core_add));
200 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
201 reg |= (0x80000000 >> (i));
202 else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
203 reg &= ~(0x80000000 >> (i));
204 out_be32((void *)GPIO_OR(core_add), reg);
206 reg = in_be32((void *)GPIO_TCR(core_add)) |
208 out_be32((void *)GPIO_TCR(core_add), reg);
210 reg = in_be32((void *)GPIO_OS(core_add+offs))
211 & ~(GPIO_MASK >> (j*2));
212 out_be32((void *)GPIO_OS(core_add+offs), reg);
213 reg = in_be32((void *)GPIO_TS(core_add+offs))
214 & ~(GPIO_MASK >> (j*2));
215 out_be32((void *)GPIO_TS(core_add+offs), reg);
219 gpio_alt_sel = GPIO_ALT1_SEL;
223 gpio_alt_sel = GPIO_ALT2_SEL;
227 gpio_alt_sel = GPIO_ALT3_SEL;
231 if (0 != gpio_alt_sel) {
232 reg = in_be32((void *)GPIO_OS(core_add+offs))
233 & ~(GPIO_MASK >> (j*2));
234 reg = reg | (gpio_alt_sel >> (j*2));
235 out_be32((void *)GPIO_OS(core_add+offs), reg);
237 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
238 reg = in_be32((void *)GPIO_TCR(core_add))
239 | (0x80000000 >> (i));
240 out_be32((void *)GPIO_TCR(core_add), reg);
241 reg = in_be32((void *)GPIO_TS(core_add+offs))
242 & ~(GPIO_MASK >> (j*2));
243 out_be32((void *)GPIO_TS(core_add+offs), reg);
245 reg = in_be32((void *)GPIO_TCR(core_add))
246 & ~(0x80000000 >> (i));
247 out_be32((void *)GPIO_TCR(core_add), reg);
248 reg = in_be32((void *)GPIO_TS(core_add+offs))
249 & ~(GPIO_MASK >> (j*2));
250 reg = reg | (gpio_alt_sel >> (j*2));
251 out_be32((void *)GPIO_TS(core_add+offs), reg);
259 #endif /* GPIO0_BASE */
260 #endif /* CONFIG_SYS_4xx_GPIO_TABLE */