2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
54 * The processor starts at 0xfffffffc and the code is executed
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
66 #include <asm-offsets.h>
68 #include <asm/ppc4xx.h>
69 #include <timestamp.h>
72 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
74 #include <ppc_asm.tmpl>
77 #include <asm/cache.h>
79 #include <asm/ppc4xx-isram.h>
81 #ifndef CONFIG_IDENT_STRING
82 #define CONFIG_IDENT_STRING ""
85 #ifdef CONFIG_SYS_INIT_DCACHE_CS
86 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
89 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
90 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
91 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
94 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
97 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
98 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
99 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
102 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
105 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
106 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
107 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
110 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
113 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
114 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
115 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
118 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
121 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
122 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
123 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
126 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
129 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
130 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
131 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
134 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
137 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
138 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
139 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
142 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
145 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
146 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
147 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
157 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
158 * used as temporary stack pointer for the primordial stack
160 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
161 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
162 EBC_BXAP_TWT_ENCODE(7) | \
163 EBC_BXAP_BCE_DISABLE | \
164 EBC_BXAP_BCT_2TRANS | \
165 EBC_BXAP_CSN_ENCODE(0) | \
166 EBC_BXAP_OEN_ENCODE(0) | \
167 EBC_BXAP_WBN_ENCODE(0) | \
168 EBC_BXAP_WBF_ENCODE(0) | \
169 EBC_BXAP_TH_ENCODE(2) | \
170 EBC_BXAP_RE_DISABLED | \
171 EBC_BXAP_SOR_NONDELAYED | \
172 EBC_BXAP_BEM_WRITEONLY | \
173 EBC_BXAP_PEN_DISABLED)
174 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
175 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
176 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
180 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
181 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
182 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
184 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
186 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
187 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
191 * Unless otherwise overriden, enable two 128MB cachable instruction regions
192 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
193 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
195 #if !defined(CONFIG_SYS_FLASH_BASE)
196 /* If not already defined, set it to the "last" 128MByte region */
197 # define CONFIG_SYS_FLASH_BASE 0xf8000000
199 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
200 # define CONFIG_SYS_ICACHE_SACR_VALUE \
201 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
203 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
204 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
206 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
207 # define CONFIG_SYS_DCACHE_SACR_VALUE \
209 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
211 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
212 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
215 #define function_prolog(func_name) .text; \
219 #define function_epilog(func_name) .type func_name,@function; \
220 .size func_name,.-func_name
222 /* We don't want the MMU yet.
225 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
228 .extern ext_bus_cntlr_init
229 #ifdef CONFIG_NAND_U_BOOT
230 .extern reconfig_tlb0
234 * Set up GOT: Global Offset Table
236 * Use r12 to access the GOT
238 #if !defined(CONFIG_NAND_SPL)
240 GOT_ENTRY(_GOT2_TABLE_)
241 GOT_ENTRY(_FIXUP_TABLE_)
244 GOT_ENTRY(_start_of_vectors)
245 GOT_ENTRY(_end_of_vectors)
246 GOT_ENTRY(transfer_to_handler)
248 GOT_ENTRY(__init_end)
250 GOT_ENTRY(__bss_start)
252 #endif /* CONFIG_NAND_SPL */
254 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
256 * NAND U-Boot image is started from offset 0
259 #if defined(CONFIG_440)
263 bl cpu_init_f /* run low-level CPU init code (from Flash) */
265 /* NOTREACHED - board_init_f() does not return */
268 #if defined(CONFIG_SYS_RAMBOOT)
270 * 4xx RAM-booting U-Boot image is started from offset 0
277 * 440 Startup -- on reset only the top 4k of the effective
278 * address space is mapped in by an entry in the instruction
279 * and data shadow TLB. The .bootpg section is located in the
280 * top 4k & does only what's necessary to map in the the rest
281 * of the boot rom. Once the boot rom is mapped in we can
282 * proceed with normal startup.
284 * NOTE: CS0 only covers the top 2MB of the effective address
288 #if defined(CONFIG_440)
289 #if !defined(CONFIG_NAND_SPL)
290 .section .bootpg,"ax"
294 /**************************************************************************/
296 /*--------------------------------------------------------------------+
297 | 440EPX BUP Change - Hardware team request
298 +--------------------------------------------------------------------*/
299 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
304 /*----------------------------------------------------------------+
305 | Core bug fix. Clear the esr
306 +-----------------------------------------------------------------*/
309 /*----------------------------------------------------------------*/
310 /* Clear and set up some registers. */
311 /*----------------------------------------------------------------*/
312 iccci r0,r0 /* NOTE: operands not used for 440 */
313 dccci r0,r0 /* NOTE: operands not used for 440 */
320 /* NOTE: 440GX adds machine check status regs */
321 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
328 /*----------------------------------------------------------------*/
330 /*----------------------------------------------------------------*/
331 /* Disable store gathering & broadcast, guarantee inst/data
332 * cache block touch, force load/store alignment
333 * (see errata 1.12: 440_33)
335 lis r1,0x0030 /* store gathering & broadcast disable */
336 ori r1,r1,0x6000 /* cache touch */
339 /*----------------------------------------------------------------*/
340 /* Initialize debug */
341 /*----------------------------------------------------------------*/
343 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
344 bne skip_debug_init /* if set, don't clear debug register */
346 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
360 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
363 #if defined (CONFIG_440SPE)
364 /*----------------------------------------------------------------+
365 | Initialize Core Configuration Reg1.
366 | a. ICDPEI: Record even parity. Normal operation.
367 | b. ICTPEI: Record even parity. Normal operation.
368 | c. DCTPEI: Record even parity. Normal operation.
369 | d. DCDPEI: Record even parity. Normal operation.
370 | e. DCUPEI: Record even parity. Normal operation.
371 | f. DCMPEI: Record even parity. Normal operation.
372 | g. FCOM: Normal operation
373 | h. MMUPEI: Record even parity. Normal operation.
374 | i. FFF: Flush only as much data as necessary.
375 | j. TCS: Timebase increments from CPU clock.
376 +-----------------------------------------------------------------*/
380 /*----------------------------------------------------------------+
381 | Reset the timebase.
382 | The previous write to CCR1 sets the timebase source.
383 +-----------------------------------------------------------------*/
388 /*----------------------------------------------------------------*/
389 /* Setup interrupt vectors */
390 /*----------------------------------------------------------------*/
391 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
393 mtspr SPRN_IVOR0,r1 /* Critical input */
395 mtspr SPRN_IVOR1,r1 /* Machine check */
397 mtspr SPRN_IVOR2,r1 /* Data storage */
399 mtspr SPRN_IVOR3,r1 /* Instruction storage */
401 mtspr SPRN_IVOR4,r1 /* External interrupt */
403 mtspr SPRN_IVOR5,r1 /* Alignment */
405 mtspr SPRN_IVOR6,r1 /* Program check */
407 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
409 mtspr SPRN_IVOR8,r1 /* System call */
411 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
413 mtspr SPRN_IVOR10,r1 /* Decrementer */
415 mtspr SPRN_IVOR13,r1 /* Data TLB error */
417 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
419 mtspr SPRN_IVOR15,r1 /* Debug */
421 /*----------------------------------------------------------------*/
422 /* Configure cache regions */
423 /*----------------------------------------------------------------*/
441 /*----------------------------------------------------------------*/
442 /* Cache victim limits */
443 /*----------------------------------------------------------------*/
444 /* floors 0, ceiling max to use the entire cache -- nothing locked
451 /*----------------------------------------------------------------+
452 |Initialize MMUCR[STID] = 0.
453 +-----------------------------------------------------------------*/
460 /*----------------------------------------------------------------*/
461 /* Clear all TLB entries -- TID = 0, TS = 0 */
462 /*----------------------------------------------------------------*/
464 #ifdef CONFIG_SYS_RAMBOOT
465 li r4,0 /* Start with TLB #0 */
467 li r4,1 /* Start with TLB #1 */
469 li r1,64 /* 64 TLB entries */
470 sub r1,r1,r4 /* calculate last TLB # */
473 #ifdef CONFIG_SYS_RAMBOOT
474 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
475 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
476 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
478 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
481 tlbnxt: addi r4,r4,1 /* Next TLB */
484 /*----------------------------------------------------------------*/
485 /* TLB entry setup -- step thru tlbtab */
486 /*----------------------------------------------------------------*/
487 #if defined(CONFIG_440SPE_REVA)
488 /*----------------------------------------------------------------*/
489 /* We have different TLB tables for revA and rev B of 440SPe */
490 /*----------------------------------------------------------------*/
502 bl tlbtab /* Get tlbtab pointer */
505 li r1,0x003f /* 64 TLB entries max */
511 #ifdef CONFIG_SYS_RAMBOOT
512 tlbre r3,r4,0 /* Read contents from TLB word #0 */
513 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
514 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
518 beq 2f /* 0 marks end */
521 tlbwe r0,r4,0 /* TLB Word 0 */
522 tlbwe r1,r4,1 /* TLB Word 1 */
523 tlbwe r2,r4,2 /* TLB Word 2 */
524 tlbnx2: addi r4,r4,1 /* Next TLB */
527 /*----------------------------------------------------------------*/
528 /* Continue from 'normal' start */
529 /*----------------------------------------------------------------*/
535 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
539 #endif /* CONFIG_440 */
542 * r3 - 1st arg to board_init(): IMMP pointer
543 * r4 - 2nd arg to board_init(): boot flag
545 #ifndef CONFIG_NAND_SPL
547 .long 0x27051956 /* U-Boot Magic Number */
548 .globl version_string
550 .ascii U_BOOT_VERSION
551 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
552 .ascii CONFIG_IDENT_STRING, "\0"
554 . = EXC_OFF_SYS_RESET
555 .globl _start_of_vectors
558 /* Critical input. */
559 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
563 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
565 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
566 #endif /* CONFIG_440 */
568 /* Data Storage exception. */
569 STD_EXCEPTION(0x300, DataStorage, UnknownException)
571 /* Instruction Storage exception. */
572 STD_EXCEPTION(0x400, InstStorage, UnknownException)
574 /* External Interrupt exception. */
575 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
577 /* Alignment exception. */
580 EXCEPTION_PROLOG(SRR0, SRR1)
585 addi r3,r1,STACK_FRAME_OVERHEAD
586 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
588 /* Program check exception */
591 EXCEPTION_PROLOG(SRR0, SRR1)
592 addi r3,r1,STACK_FRAME_OVERHEAD
593 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
597 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
598 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
599 STD_EXCEPTION(0xa00, APU, UnknownException)
601 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
604 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
605 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
607 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
608 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
609 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
611 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
613 .globl _end_of_vectors
620 /*****************************************************************************/
621 #if defined(CONFIG_440)
623 /*----------------------------------------------------------------*/
624 /* Clear and set up some registers. */
625 /*----------------------------------------------------------------*/
628 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
629 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
631 mtspr SPRN_TSR,r1 /* clear all timer exception status */
632 mtspr SPRN_TCR,r0 /* disable all */
633 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
634 mtxer r0 /* clear integer exception register */
636 /*----------------------------------------------------------------*/
637 /* Debug setup -- some (not very good) ice's need an event*/
638 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
639 /* value you need in this case 0x8cff 0000 should do the trick */
640 /*----------------------------------------------------------------*/
641 #if defined(CONFIG_SYS_INIT_DBCR)
644 mtspr SPRN_DBSR,r1 /* Clear all status bits */
645 lis r0,CONFIG_SYS_INIT_DBCR@h
646 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
651 /*----------------------------------------------------------------*/
652 /* Setup the internal SRAM */
653 /*----------------------------------------------------------------*/
656 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
657 /* Clear Dcache to use as RAM */
658 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
659 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
660 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
661 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
662 rlwinm. r5,r4,0,27,31
674 * Lock the init-ram/stack in d-cache, so that other regions
675 * may use d-cache as well
676 * Note, that this current implementation locks exactly 4k
677 * of d-cache, so please make sure that you don't define a
678 * bigger init-ram area. Take a look at the lwmon5 440EPx
679 * implementation as a reference.
683 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
699 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
701 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
702 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
703 /* not all PPC's have internal SRAM usable as L2-cache */
704 #if defined(CONFIG_440GX) || \
705 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
706 defined(CONFIG_460SX)
707 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
708 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
709 defined(CONFIG_APM821XX)
711 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
712 mtdcr L2_CACHE_CFG,r1
718 and r1,r1,r2 /* Disable parity check */
721 and r1,r1,r2 /* Disable pwr mgmt */
724 lis r1,0x8000 /* BAS = 8000_0000 */
725 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
726 ori r1,r1,0x0980 /* first 64k */
727 mtdcr ISRAM0_SB0CR,r1
729 ori r1,r1,0x0980 /* second 64k */
730 mtdcr ISRAM0_SB1CR,r1
732 ori r1,r1, 0x0980 /* third 64k */
733 mtdcr ISRAM0_SB2CR,r1
735 ori r1,r1, 0x0980 /* fourth 64k */
736 mtdcr ISRAM0_SB3CR,r1
737 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
738 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
739 lis r1,0x0000 /* BAS = X_0000_0000 */
740 ori r1,r1,0x0984 /* first 64k */
741 mtdcr ISRAM0_SB0CR,r1
743 ori r1,r1,0x0984 /* second 64k */
744 mtdcr ISRAM0_SB1CR,r1
746 ori r1,r1, 0x0984 /* third 64k */
747 mtdcr ISRAM0_SB2CR,r1
749 ori r1,r1, 0x0984 /* fourth 64k */
750 mtdcr ISRAM0_SB3CR,r1
751 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
752 defined(CONFIG_APM821XX)
756 and r1,r1,r2 /* Disable parity check */
759 and r1,r1,r2 /* Disable pwr mgmt */
762 lis r1,0x0004 /* BAS = 4_0004_0000 */
763 ori r1,r1,ISRAM1_SIZE /* ocm size */
764 mtdcr ISRAM1_SB0CR,r1
766 #elif defined(CONFIG_460SX)
767 lis r1,0x0000 /* BAS = 0000_0000 */
768 ori r1,r1,0x0B84 /* first 128k */
769 mtdcr ISRAM0_SB0CR,r1
771 ori r1,r1,0x0B84 /* second 128k */
772 mtdcr ISRAM0_SB1CR,r1
774 ori r1,r1, 0x0B84 /* third 128k */
775 mtdcr ISRAM0_SB2CR,r1
777 ori r1,r1, 0x0B84 /* fourth 128k */
778 mtdcr ISRAM0_SB3CR,r1
779 #elif defined(CONFIG_440GP)
780 ori r1,r1,0x0380 /* 8k rw */
781 mtdcr ISRAM0_SB0CR,r1
782 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
784 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
786 /*----------------------------------------------------------------*/
787 /* Setup the stack in internal SRAM */
788 /*----------------------------------------------------------------*/
789 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
790 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
793 stwu r0,-4(r1) /* Terminate call chain */
795 stwu r1,-8(r1) /* Save back chain and move SP */
796 lis r0,RESET_VECTOR@h /* Address of reset vector */
797 ori r0,r0, RESET_VECTOR@l
798 stwu r1,-8(r1) /* Save back chain and move SP */
799 stw r0,+12(r1) /* Save return addr (underflow vect) */
801 #ifdef CONFIG_NAND_SPL
802 bl nand_boot_common /* will not return */
806 bl cpu_init_f /* run low-level CPU init code (from Flash) */
808 /* NOTREACHED - board_init_f() does not return */
811 #endif /* CONFIG_440 */
813 /*****************************************************************************/
815 /*----------------------------------------------------------------------- */
816 /* Set up some machine state registers. */
817 /*----------------------------------------------------------------------- */
818 addi r0,r0,0x0000 /* initialize r0 to zero */
819 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
820 mttcr r0 /* timer control register */
821 mtexier r0 /* disable all interrupts */
822 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
823 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
824 mtdbsr r4 /* clear/reset the dbsr */
825 mtexisr r4 /* clear all pending interrupts */
827 mtexier r4 /* enable critical exceptions */
828 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
829 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
830 mtiocr r4 /* since bit not used) & DRC to latch */
831 /* data bus on rising edge of CAS */
832 /*----------------------------------------------------------------------- */
834 /*----------------------------------------------------------------------- */
836 /*----------------------------------------------------------------------- */
837 /* Invalidate i-cache and d-cache TAG arrays. */
838 /*----------------------------------------------------------------------- */
839 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
840 addi r4,0,1024 /* 1/4 of I-cache */
845 addic. r3,r3,-16 /* move back one cache line */
846 bne ..cloop /* loop back to do rest until r3 = 0 */
849 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
850 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
853 /* first copy IOP480 register base address into r3 */
854 addis r3,0,0x5000 /* IOP480 register base address hi */
855 /* ori r3,r3,0x0000 / IOP480 register base address lo */
858 /* use r4 as the working variable */
859 /* turn on CS3 (LOCCTL.7) */
860 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
861 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
862 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
865 #ifdef CONFIG_DASA_SIM
866 /* use r4 as the working variable */
867 /* turn on MA17 (LOCCTL.7) */
868 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
869 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
870 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
873 /* turn on MA16..13 (LCS0BRD.12 = 0) */
874 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
875 andi. r4,r4,0xefff /* make bit 12 = 0 */
876 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
878 /* make sure above stores all comlete before going on */
881 /* last thing, set local init status done bit (DEVINIT.31) */
882 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
883 oris r4,r4,0x8000 /* make bit 31 = 1 */
884 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
886 /* clear all pending interrupts and disable all interrupts */
887 li r4,-1 /* set p1 to 0xffffffff */
888 stw r4,0x1b0(r3) /* clear all pending interrupts */
889 stw r4,0x1b8(r3) /* clear all pending interrupts */
890 li r4,0 /* set r4 to 0 */
891 stw r4,0x1b4(r3) /* disable all interrupts */
892 stw r4,0x1bc(r3) /* disable all interrupts */
894 /* make sure above stores all comlete before going on */
897 /* Set-up icache cacheability. */
898 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
899 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
903 /* Set-up dcache cacheability. */
904 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
905 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
908 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
909 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
910 li r0, 0 /* Make room for stack frame header and */
911 stwu r0, -4(r1) /* clear final stack frame so that */
912 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
914 GET_GOT /* initialize GOT access */
916 bl board_init_f /* run first part of init code (from Flash) */
917 /* NOTREACHED - board_init_f() does not return */
919 #endif /* CONFIG_IOP480 */
921 /*****************************************************************************/
922 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
923 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
924 defined(CONFIG_405EX) || defined(CONFIG_405)
925 /*----------------------------------------------------------------------- */
926 /* Clear and set up some registers. */
927 /*----------------------------------------------------------------------- */
929 #if !defined(CONFIG_405EX)
933 * On 405EX, completely clearing the SGR leads to PPC hangup
934 * upon PCIe configuration access. The PCIe memory regions
935 * need to be guarded!
942 mtesr r4 /* clear Exception Syndrome Reg */
943 mttcr r4 /* clear Timer Control Reg */
944 mtxer r4 /* clear Fixed-Point Exception Reg */
945 mtevpr r4 /* clear Exception Vector Prefix Reg */
946 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
947 /* dbsr is cleared by setting bits to 1) */
948 mtdbsr r4 /* clear/reset the dbsr */
950 /* Invalidate the i- and d-caches. */
954 /* Set-up icache cacheability. */
955 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
956 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
960 /* Set-up dcache cacheability. */
961 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
962 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
965 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
966 && !defined (CONFIG_XILINX_405)
967 /*----------------------------------------------------------------------- */
968 /* Tune the speed and size for flash CS0 */
969 /*----------------------------------------------------------------------- */
970 bl ext_bus_cntlr_init
973 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
975 * For boards that don't have OCM and can't use the data cache
976 * for their primordial stack, setup stack here directly after the
977 * SDRAM is initialized in ext_bus_cntlr_init.
979 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
980 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
982 li r0, 0 /* Make room for stack frame header and */
983 stwu r0, -4(r1) /* clear final stack frame so that */
984 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
986 * Set up a dummy frame to store reset vector as return address.
987 * this causes stack underflow to reset board.
989 stwu r1, -8(r1) /* Save back chain and move SP */
990 lis r0, RESET_VECTOR@h /* Address of reset vector */
991 ori r0, r0, RESET_VECTOR@l
992 stwu r1, -8(r1) /* Save back chain and move SP */
993 stw r0, +12(r1) /* Save return addr (underflow vect) */
994 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
996 #if defined(CONFIG_405EP)
997 /*----------------------------------------------------------------------- */
998 /* DMA Status, clear to come up clean */
999 /*----------------------------------------------------------------------- */
1000 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
1004 bl ppc405ep_init /* do ppc405ep specific init */
1005 #endif /* CONFIG_405EP */
1007 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1008 #if defined(CONFIG_405EZ)
1009 /********************************************************************
1010 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1011 *******************************************************************/
1013 * We can map the OCM on the PLB3, so map it at
1014 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1016 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1017 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1018 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1019 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1020 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1021 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1024 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1025 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1026 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1027 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1028 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1029 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1030 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1031 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1032 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1033 mtdcr OCM0_DISDPC,r3
1036 #else /* CONFIG_405EZ */
1037 /********************************************************************
1038 * Setup OCM - On Chip Memory
1039 *******************************************************************/
1043 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1044 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1045 and r3, r3, r0 /* disable data-side IRAM */
1046 and r4, r4, r0 /* disable data-side IRAM */
1047 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1048 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1051 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1052 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1053 mtdcr OCM0_DSARC, r3
1054 addis r4, 0, 0xC000 /* OCM data area enabled */
1055 mtdcr OCM0_DSCNTL, r4
1057 #endif /* CONFIG_405EZ */
1060 /*----------------------------------------------------------------------- */
1061 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1062 /*----------------------------------------------------------------------- */
1063 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1065 mtdcr EBC0_CFGADDR, r4
1066 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1067 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1068 mtdcr EBC0_CFGDATA, r4
1071 mtdcr EBC0_CFGADDR, r4
1072 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1073 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1074 mtdcr EBC0_CFGDATA, r4
1077 * Enable the data cache for the 128MB storage access control region
1078 * at CONFIG_SYS_INIT_RAM_ADDR.
1081 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1082 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1086 * Preallocate data cache lines to be used to avoid a subsequent
1087 * cache miss and an ensuing machine check exception when exceptions
1092 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1093 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1095 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1096 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1099 * Convert the size, in bytes, to the number of cache lines/blocks
1102 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1103 srwi r5, r4, L1_CACHE_SHIFT
1109 /* Preallocate the computed number of cache blocks. */
1110 ..alloc_dcache_block:
1112 addi r3, r3, L1_CACHE_BYTES
1113 bdnz ..alloc_dcache_block
1117 * Load the initial stack pointer and data area and convert the size,
1118 * in bytes, to the number of words to initialize to a known value.
1120 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1121 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1123 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1124 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1127 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1128 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1130 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1131 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1138 * Make room for stack frame header and clear final stack frame so
1139 * that stack backtraces terminate cleanly.
1145 * Set up a dummy frame to store reset vector as return address.
1146 * this causes stack underflow to reset board.
1148 stwu r1, -8(r1) /* Save back chain and move SP */
1149 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1150 ori r0, r0, RESET_VECTOR@l
1151 stwu r1, -8(r1) /* Save back chain and move SP */
1152 stw r0, +12(r1) /* Save return addr (underflow vect) */
1154 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1155 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1160 /* Set up Stack at top of OCM */
1161 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1162 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1164 /* Set up a zeroized stack frame so that backtrace works right */
1170 * Set up a dummy frame to store reset vector as return address.
1171 * this causes stack underflow to reset board.
1173 stwu r1, -8(r1) /* Save back chain and move SP */
1174 lis r0, RESET_VECTOR@h /* Address of reset vector */
1175 ori r0, r0, RESET_VECTOR@l
1176 stwu r1, -8(r1) /* Save back chain and move SP */
1177 stw r0, +12(r1) /* Save return addr (underflow vect) */
1178 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1180 #ifdef CONFIG_NAND_SPL
1181 bl nand_boot_common /* will not return */
1183 GET_GOT /* initialize GOT access */
1185 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1187 bl board_init_f /* run first part of init code (from Flash) */
1188 /* NOTREACHED - board_init_f() does not return */
1190 #endif /* CONFIG_NAND_SPL */
1192 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1193 /*----------------------------------------------------------------------- */
1196 #ifndef CONFIG_NAND_SPL
1198 * This code finishes saving the registers to the exception frame
1199 * and jumps to the appropriate handler for the exception.
1200 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1202 .globl transfer_to_handler
1203 transfer_to_handler:
1213 andi. r24,r23,0x3f00 /* get vector offset */
1217 mtspr SPRG2,r22 /* r1 is now kernel sp */
1218 lwz r24,0(r23) /* virtual address of handler */
1219 lwz r23,4(r23) /* where to go when done */
1224 rfi /* jump to handler, enable MMU */
1227 mfmsr r28 /* Disable interrupts */
1231 SYNC /* Some chip revs need this... */
1246 lwz r2,_NIP(r1) /* Restore environment */
1257 mfmsr r28 /* Disable interrupts */
1261 SYNC /* Some chip revs need this... */
1276 lwz r2,_NIP(r1) /* Restore environment */
1288 mfmsr r28 /* Disable interrupts */
1292 SYNC /* Some chip revs need this... */
1307 lwz r2,_NIP(r1) /* Restore environment */
1309 mtspr SPRN_MCSRR0,r2
1310 mtspr SPRN_MCSRR1,r0
1316 #endif /* CONFIG_440 */
1324 /*------------------------------------------------------------------------------- */
1325 /* Function: out16 */
1326 /* Description: Output 16 bits */
1327 /*------------------------------------------------------------------------------- */
1333 /*------------------------------------------------------------------------------- */
1334 /* Function: out16r */
1335 /* Description: Byte reverse and output 16 bits */
1336 /*------------------------------------------------------------------------------- */
1342 /*------------------------------------------------------------------------------- */
1343 /* Function: out32r */
1344 /* Description: Byte reverse and output 32 bits */
1345 /*------------------------------------------------------------------------------- */
1351 /*------------------------------------------------------------------------------- */
1352 /* Function: in16 */
1353 /* Description: Input 16 bits */
1354 /*------------------------------------------------------------------------------- */
1360 /*------------------------------------------------------------------------------- */
1361 /* Function: in16r */
1362 /* Description: Input 16 bits and byte reverse */
1363 /*------------------------------------------------------------------------------- */
1369 /*------------------------------------------------------------------------------- */
1370 /* Function: in32r */
1371 /* Description: Input 32 bits and byte reverse */
1372 /*------------------------------------------------------------------------------- */
1379 * void relocate_code (addr_sp, gd, addr_moni)
1381 * This "function" does not return, instead it continues in RAM
1382 * after relocating the monitor code.
1384 * r3 = Relocated stack pointer
1385 * r4 = Relocated global data pointer
1386 * r5 = Relocated text pointer
1388 .globl relocate_code
1390 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1392 * We need to flush the initial global data (gd_t) before the dcache
1393 * will be invalidated.
1396 /* Save registers */
1401 /* Flush initial global data range */
1403 addi r4, r4, GENERATED_GBL_DATA_SIZE@l
1404 bl flush_dcache_range
1406 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1408 * Undo the earlier data cache set-up for the primordial stack and
1409 * data area. First, invalidate the data cache and then disable data
1410 * cacheability for that area. Finally, restore the EBC values, if
1414 /* Invalidate the primordial stack and data area in cache */
1415 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1416 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1418 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1419 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1422 bl invalidate_dcache_range
1424 /* Disable cacheability for the region */
1426 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1427 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1431 /* Restore the EBC parameters */
1433 mtdcr EBC0_CFGADDR, r3
1435 ori r3, r3, PBxAP_VAL@l
1436 mtdcr EBC0_CFGDATA, r3
1439 mtdcr EBC0_CFGADDR, r3
1441 ori r3, r3, PBxCR_VAL@l
1442 mtdcr EBC0_CFGDATA, r3
1443 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1445 /* Restore registers */
1449 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1451 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1453 * Unlock the previously locked d-cache
1457 /* set TFLOOR/NFLOOR to 0 again */
1474 /* Invalidate data cache, now no longer our stack */
1478 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1481 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1482 * to speed up the boot process. Now this cache needs to be disabled.
1484 #if defined(CONFIG_440)
1485 /* Clear all potential pending exceptions */
1488 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1489 tlbre r0,r1,0x0002 /* Read contents */
1490 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1491 tlbwe r0,r1,0x0002 /* Save it out */
1494 #endif /* defined(CONFIG_440) */
1495 mr r1, r3 /* Set new stack pointer */
1496 mr r9, r4 /* Save copy of Init Data pointer */
1497 mr r10, r5 /* Save copy of Destination Address */
1500 mr r3, r5 /* Destination Address */
1501 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1502 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1503 lwz r5, GOT(__init_end)
1505 li r6, L1_CACHE_BYTES /* Cache Line Size */
1510 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1516 /* First our own GOT */
1518 /* then the one used by the C code */
1528 beq cr1,4f /* In place copy is not necessary */
1529 beq 7f /* Protect against 0 count */
1548 * Now flush the cache: note that we must start from a cache aligned
1549 * address. Otherwise we might miss one cache line.
1553 beq 7f /* Always flush prefetch queue in any case */
1561 sync /* Wait for all dcbst to complete on bus */
1567 7: sync /* Wait for all icbi to complete on bus */
1571 * We are done. Do not return, instead branch to second part of board
1572 * initialization, now running from RAM.
1575 addi r0, r10, in_ram - _start + _START_OFFSET
1577 blr /* NEVER RETURNS! */
1582 * Relocation Function, r12 point to got2+0x8000
1584 * Adjust got2 pointers, no need to check for 0, this code
1585 * already puts a few entries in the table.
1587 li r0,__got2_entries@sectoff@l
1588 la r3,GOT(_GOT2_TABLE_)
1589 lwz r11,GOT(_GOT2_TABLE_)
1601 * Now adjust the fixups and the pointers to the fixups
1602 * in case we need to move ourselves again.
1604 li r0,__fixup_entries@sectoff@l
1605 lwz r3,GOT(_FIXUP_TABLE_)
1621 * Now clear BSS segment
1623 lwz r3,GOT(__bss_start)
1646 mr r3, r9 /* Init Data pointer */
1647 mr r4, r10 /* Destination Address */
1651 * Copy exception vector code to low memory
1654 * r7: source address, r8: end address, r9: target address
1658 mflr r4 /* save link register */
1660 lwz r7, GOT(_start_of_vectors)
1661 lwz r8, GOT(_end_of_vectors)
1663 li r9, 0x100 /* reset vector always at 0x100 */
1666 bgelr /* return if r7>=r8 - just in case */
1676 * relocate `hdlr' and `int_return' entries
1678 li r7, .L_MachineCheck - _start + _START_OFFSET
1679 li r8, Alignment - _start + _START_OFFSET
1682 addi r7, r7, 0x100 /* next exception vector */
1686 li r7, .L_Alignment - _start + _START_OFFSET
1689 li r7, .L_ProgramCheck - _start + _START_OFFSET
1693 li r7, .L_FPUnavailable - _start + _START_OFFSET
1696 li r7, .L_Decrementer - _start + _START_OFFSET
1699 li r7, .L_APU - _start + _START_OFFSET
1702 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1705 li r7, .L_DataTLBError - _start + _START_OFFSET
1707 #else /* CONFIG_440 */
1708 li r7, .L_PIT - _start + _START_OFFSET
1711 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1714 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1716 #endif /* CONFIG_440 */
1718 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1721 #if !defined(CONFIG_440)
1722 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1723 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1724 mtmsr r7 /* change MSR */
1727 b __440_msr_continue
1730 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1731 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1739 mtlr r4 /* restore link register */
1742 #if defined(CONFIG_440)
1743 /*----------------------------------------------------------------------------+
1745 +----------------------------------------------------------------------------*/
1746 function_prolog(dcbz_area)
1747 rlwinm. r5,r4,0,27,31
1748 rlwinm r5,r4,27,5,31
1757 function_epilog(dcbz_area)
1758 #endif /* CONFIG_440 */
1759 #endif /* CONFIG_NAND_SPL */
1761 /*------------------------------------------------------------------------------- */
1763 /* Description: Input 8 bits */
1764 /*------------------------------------------------------------------------------- */
1770 /*------------------------------------------------------------------------------- */
1771 /* Function: out8 */
1772 /* Description: Output 8 bits */
1773 /*------------------------------------------------------------------------------- */
1779 /*------------------------------------------------------------------------------- */
1780 /* Function: out32 */
1781 /* Description: Output 32 bits */
1782 /*------------------------------------------------------------------------------- */
1788 /*------------------------------------------------------------------------------- */
1789 /* Function: in32 */
1790 /* Description: Input 32 bits */
1791 /*------------------------------------------------------------------------------- */
1797 /**************************************************************************/
1798 /* PPC405EP specific stuff */
1799 /**************************************************************************/
1803 #ifdef CONFIG_BUBINGA
1805 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1806 * function) to support FPGA and NVRAM accesses below.
1809 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1810 ori r3,r3,GPIO0_OSRH@l
1811 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1812 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1815 ori r3,r3,GPIO0_OSRL@l
1816 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1817 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1820 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1821 ori r3,r3,GPIO0_ISR1H@l
1822 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1823 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1825 lis r3,GPIO0_ISR1L@h
1826 ori r3,r3,GPIO0_ISR1L@l
1827 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1828 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1831 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1832 ori r3,r3,GPIO0_TSRH@l
1833 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1834 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1837 ori r3,r3,GPIO0_TSRL@l
1838 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1839 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1842 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1843 ori r3,r3,GPIO0_TCR@l
1844 lis r4,CONFIG_SYS_GPIO0_TCR@h
1845 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1848 li r3,PB1AP /* program EBC bank 1 for RTC access */
1849 mtdcr EBC0_CFGADDR,r3
1850 lis r3,CONFIG_SYS_EBC_PB1AP@h
1851 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1852 mtdcr EBC0_CFGDATA,r3
1854 mtdcr EBC0_CFGADDR,r3
1855 lis r3,CONFIG_SYS_EBC_PB1CR@h
1856 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1857 mtdcr EBC0_CFGDATA,r3
1859 li r3,PB1AP /* program EBC bank 1 for RTC access */
1860 mtdcr EBC0_CFGADDR,r3
1861 lis r3,CONFIG_SYS_EBC_PB1AP@h
1862 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1863 mtdcr EBC0_CFGDATA,r3
1865 mtdcr EBC0_CFGADDR,r3
1866 lis r3,CONFIG_SYS_EBC_PB1CR@h
1867 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1868 mtdcr EBC0_CFGDATA,r3
1870 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1871 mtdcr EBC0_CFGADDR,r3
1872 lis r3,CONFIG_SYS_EBC_PB4AP@h
1873 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1874 mtdcr EBC0_CFGDATA,r3
1876 mtdcr EBC0_CFGADDR,r3
1877 lis r3,CONFIG_SYS_EBC_PB4CR@h
1878 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1879 mtdcr EBC0_CFGDATA,r3
1883 !-----------------------------------------------------------------------
1884 ! Check to see if chip is in bypass mode.
1885 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1886 ! CPU reset Otherwise, skip this step and keep going.
1887 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1888 ! will not be fast enough for the SDRAM (min 66MHz)
1889 !-----------------------------------------------------------------------
1891 mfdcr r5, CPC0_PLLMR1
1892 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1895 beq pll_done /* if SSCS =b'1' then PLL has */
1896 /* already been set */
1897 /* and CPU has been reset */
1898 /* so skip to next section */
1900 #ifdef CONFIG_BUBINGA
1902 !-----------------------------------------------------------------------
1903 ! Read NVRAM to get value to write in PLLMR.
1904 ! If value has not been correctly saved, write default value
1905 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1906 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1908 ! WARNING: This code assumes the first three words in the nvram_t
1909 ! structure in openbios.h. Changing the beginning of
1910 ! the structure will break this code.
1912 !-----------------------------------------------------------------------
1914 addis r3,0,NVRAM_BASE@h
1915 addi r3,r3,NVRAM_BASE@l
1918 addis r5,0,NVRVFY1@h
1919 addi r5,r5,NVRVFY1@l
1920 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1924 addis r5,0,NVRVFY2@h
1925 addi r5,r5,NVRVFY2@l
1926 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1928 addi r3,r3,8 /* Skip over conf_size */
1929 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1930 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1931 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1932 cmpi cr0,0,r5,1 /* See if PLL is locked */
1935 #endif /* CONFIG_BUBINGA */
1939 andi. r5, r4, CPC0_BOOT_SEP@l
1940 bne strap_1 /* serial eeprom present */
1941 addis r5,0,CPLD_REG0_ADDR@h
1942 ori r5,r5,CPLD_REG0_ADDR@l
1945 #endif /* CONFIG_TAIHU */
1947 #if defined(CONFIG_ZEUS)
1949 andi. r5, r4, CPC0_BOOT_SEP@l
1950 bne strap_1 /* serial eeprom present */
1957 mfdcr r3, CPC0_PLLMR0
1958 mfdcr r4, CPC0_PLLMR1
1962 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1963 ori r3,r3,PLLMR0_DEFAULT@l /* */
1964 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1965 ori r4,r4,PLLMR1_DEFAULT@l /* */
1970 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1971 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1972 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1973 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1976 mfdcr r3, CPC0_PLLMR0
1977 mfdcr r4, CPC0_PLLMR1
1978 #endif /* CONFIG_TAIHU */
1981 b pll_write /* Write the CPC0_PLLMR with new value */
1985 !-----------------------------------------------------------------------
1986 ! Clear Soft Reset Register
1987 ! This is needed to enable PCI if not booting from serial EPROM
1988 !-----------------------------------------------------------------------
1998 blr /* return to main code */
2001 !-----------------------------------------------------------------------------
2002 ! Function: pll_write
2003 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2005 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2007 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2008 ! 4. PLL Reset is cleared
2009 ! 5. Wait 100us for PLL to lock
2010 ! 6. A core reset is performed
2011 ! Input: r3 = Value to write to CPC0_PLLMR0
2012 ! Input: r4 = Value to write to CPC0_PLLMR1
2014 !-----------------------------------------------------------------------------
2020 ori r5,r5,0x0101 /* Stop the UART clocks */
2021 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2023 mfdcr r5, CPC0_PLLMR1
2024 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2025 mtdcr CPC0_PLLMR1,r5
2026 oris r5,r5,0x4000 /* Set PLL Reset */
2027 mtdcr CPC0_PLLMR1,r5
2029 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2030 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2031 oris r5,r5,0x4000 /* Set PLL Reset */
2032 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2033 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2034 mtdcr CPC0_PLLMR1,r5
2037 ! Wait min of 100us for PLL to lock.
2038 ! See CMOS 27E databook for more info.
2039 ! At 200MHz, that means waiting 20,000 instructions
2041 addi r3,0,20000 /* 2000 = 0x4e20 */
2046 oris r5,r5,0x8000 /* Enable PLL */
2047 mtdcr CPC0_PLLMR1,r5 /* Engage */
2050 * Reset CPU to guarantee timings are OK
2051 * Not sure if this is needed...
2054 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2055 /* execution will continue from the poweron */
2056 /* vector of 0xfffffffc */
2057 #endif /* CONFIG_405EP */
2059 #if defined(CONFIG_440)
2060 /*----------------------------------------------------------------------------+
2062 +----------------------------------------------------------------------------*/
2063 function_prolog(mttlb3)
2066 function_epilog(mttlb3)
2068 /*----------------------------------------------------------------------------+
2070 +----------------------------------------------------------------------------*/
2071 function_prolog(mftlb3)
2074 function_epilog(mftlb3)
2076 /*----------------------------------------------------------------------------+
2078 +----------------------------------------------------------------------------*/
2079 function_prolog(mttlb2)
2082 function_epilog(mttlb2)
2084 /*----------------------------------------------------------------------------+
2086 +----------------------------------------------------------------------------*/
2087 function_prolog(mftlb2)
2090 function_epilog(mftlb2)
2092 /*----------------------------------------------------------------------------+
2094 +----------------------------------------------------------------------------*/
2095 function_prolog(mttlb1)
2098 function_epilog(mttlb1)
2100 /*----------------------------------------------------------------------------+
2102 +----------------------------------------------------------------------------*/
2103 function_prolog(mftlb1)
2106 function_epilog(mftlb1)
2107 #endif /* CONFIG_440 */
2109 #if defined(CONFIG_NAND_SPL)
2111 * void nand_boot_relocate(dst, src, bytes)
2113 * r3 = Destination address to copy code to (in SDRAM)
2114 * r4 = Source address to copy code from
2115 * r5 = size to copy in bytes
2123 * Copy SPL from icache into SDRAM
2135 * Calculate "corrected" link register, so that we "continue"
2136 * in execution in destination range
2138 sub r3,r7,r6 /* r3 = src - dst */
2139 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2145 * First initialize SDRAM. It has to be available *before* calling
2148 lis r3,CONFIG_SYS_SDRAM_BASE@h
2149 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2153 * Now copy the 4k SPL code into SDRAM and continue execution
2156 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2157 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2158 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2159 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2160 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2161 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2162 bl nand_boot_relocate
2165 * We're running from SDRAM now!!!
2167 * It is necessary for 4xx systems to relocate from running at
2168 * the original location (0xfffffxxx) to somewhere else (SDRAM
2169 * preferably). This is because CS0 needs to be reconfigured for
2170 * NAND access. And we can't reconfigure this CS when currently
2171 * "running" from it.
2175 * Finally call nand_boot() to load main NAND U-Boot image from
2176 * NAND and jump to it.
2178 bl nand_boot /* will not return */
2179 #endif /* CONFIG_NAND_SPL */