2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/config_mpc85xx.h>
12 #define CONFIG_SYS_FSL_DDR
16 #include <asm/config_mpc86xx.h>
17 #define CONFIG_SYS_FSL_DDR
21 #define CONFIG_SYS_FSL_DDR
24 #ifndef HWCONFIG_BUFFER_SIZE
25 #define HWCONFIG_BUFFER_SIZE 256
28 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
29 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
30 # ifndef CONFIG_HARD_SPI
31 # define CONFIG_HARD_SPI
36 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
37 #define CONFIG_SYS_BOOT_GET_CMDLINE
38 #define CONFIG_SYS_BOOT_GET_KBD
40 #ifndef CONFIG_MAX_MEM_MAPPED
41 #if defined(CONFIG_4xx) || \
42 defined(CONFIG_E500) || \
43 defined(CONFIG_MPC86xx) || \
45 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
47 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
51 /* Check if boards need to enable FSL DMA engine for SDRAM init */
52 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
53 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
54 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
55 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
56 #define CONFIG_FSL_DMA
61 * Provide a default boot page translation virtual address that lines up with
62 * Freescale's default e500 reset page.
64 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
65 #ifndef CONFIG_BPTR_VIRT_ADDR
66 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
71 * SEC (crypto unit) major compatible version determination
73 #if defined(CONFIG_MPC83xx)
74 #define CONFIG_SYS_FSL_SEC_BE
75 #define CONFIG_SYS_FSL_SEC_COMPAT 2
78 /* Since so many PPC SOCs have a semi-common LBC, define this here */
79 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
80 defined(CONFIG_MPC83xx)
81 #if !defined(CONFIG_FSL_IFC)
82 #define CONFIG_FSL_LBC
86 /* The TSEC driver uses the PHYLIB infrastructure */
88 #if defined(CONFIG_TSEC_ENET)
91 #include <config_phylib_all_drivers.h>
92 #endif /* TSEC_ENET */
93 #endif /* !CONFIG_PHYLIB */
95 /* The FMAN driver uses the PHYLIB infrastructure */
96 #if defined(CONFIG_FMAN_ENET)
100 /* All PPC boards must swap IDE bytes */
101 #define CONFIG_IDE_SWAP_IO
103 #if defined(CONFIG_DM_SERIAL)
105 * TODO: Convert this to a clock driver exists that can give us the UART
108 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
111 #endif /* _ASM_CONFIG_H_ */