2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
27 #define CONFIG_SYS_FSL_SEC_BE
28 #define CONFIG_SYS_FSL_SFP_BE
29 #define CONFIG_SYS_FSL_SEC_MON_BE
31 /* Number of TLB CAM entries we have on FSL Book-E chips */
32 #if defined(CONFIG_E500MC)
33 #define CONFIG_SYS_NUM_TLBCAMS 64
34 #elif defined(CONFIG_E500)
35 #define CONFIG_SYS_NUM_TLBCAMS 16
38 #if defined(CONFIG_ARCH_MPC8536)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 12
41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
42 #define CONFIG_SYS_FSL_SEC_COMPAT 2
43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
44 #define CONFIG_SYS_FSL_ERRATUM_A004508
45 #define CONFIG_SYS_FSL_ERRATUM_A005125
47 #elif defined(CONFIG_ARCH_MPC8540)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 8
50 #define CONFIG_SYS_FSL_DDRC_GEN1
51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
53 #elif defined(CONFIG_ARCH_MPC8541)
54 #define CONFIG_MAX_CPUS 1
55 #define CONFIG_SYS_FSL_NUM_LAWS 8
56 #define CONFIG_SYS_FSL_DDRC_GEN1
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_ARCH_MPC8544)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_DDRC_GEN2
64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
65 #define CONFIG_SYS_FSL_SEC_COMPAT 2
66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
67 #define CONFIG_SYS_FSL_ERRATUM_A005125
69 #elif defined(CONFIG_ARCH_MPC8548)
70 #define CONFIG_MAX_CPUS 1
71 #define CONFIG_SYS_FSL_NUM_LAWS 10
72 #define CONFIG_SYS_FSL_DDRC_GEN2
73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
74 #define CONFIG_SYS_FSL_SEC_COMPAT 2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82 #define CONFIG_SYS_FSL_RMU
83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
84 #define CONFIG_SYS_FSL_ERRATUM_A005125
85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
88 #elif defined(CONFIG_ARCH_MPC8555)
89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_FSL_SEC_COMPAT 2
93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
95 #elif defined(CONFIG_ARCH_MPC8560)
96 #define CONFIG_MAX_CPUS 1
97 #define CONFIG_SYS_FSL_NUM_LAWS 8
98 #define CONFIG_SYS_FSL_DDRC_GEN1
99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
101 #elif defined(CONFIG_ARCH_MPC8568)
102 #define CONFIG_MAX_CPUS 1
103 #define CONFIG_SYS_FSL_NUM_LAWS 10
104 #define CONFIG_SYS_FSL_DDRC_GEN2
105 #define CONFIG_SYS_FSL_SEC_COMPAT 2
106 #define QE_MURAM_SIZE 0x10000UL
107 #define MAX_QE_RISC 2
108 #define QE_NUM_OF_SNUM 28
109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113 #define CONFIG_SYS_FSL_RMU
114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
116 #elif defined(CONFIG_ARCH_MPC8569)
117 #define CONFIG_MAX_CPUS 1
118 #define CONFIG_SYS_FSL_NUM_LAWS 10
119 #define CONFIG_SYS_FSL_SEC_COMPAT 2
120 #define QE_MURAM_SIZE 0x20000UL
121 #define MAX_QE_RISC 4
122 #define QE_NUM_OF_SNUM 46
123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
127 #define CONFIG_SYS_FSL_RMU
128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
129 #define CONFIG_SYS_FSL_ERRATUM_A004508
130 #define CONFIG_SYS_FSL_ERRATUM_A005125
132 #elif defined(CONFIG_ARCH_MPC8572)
133 #define CONFIG_MAX_CPUS 2
134 #define CONFIG_SYS_FSL_NUM_LAWS 12
135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
136 #define CONFIG_SYS_FSL_SEC_COMPAT 2
137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
140 #define CONFIG_SYS_FSL_ERRATUM_A004508
141 #define CONFIG_SYS_FSL_ERRATUM_A005125
143 #elif defined(CONFIG_ARCH_P1010)
144 #define CONFIG_MAX_CPUS 1
145 #define CONFIG_FSL_SDHC_V2_3
146 #define CONFIG_SYS_FSL_NUM_LAWS 12
147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
148 #define CONFIG_TSECV2
149 #define CONFIG_SYS_FSL_SEC_COMPAT 4
150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151 #define CONFIG_NUM_DDR_CONTROLLERS 1
152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
161 #define CONFIG_SYS_FSL_ERRATUM_A005125
162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
163 #define CONFIG_SYS_FSL_ERRATUM_A004508
164 #define CONFIG_SYS_FSL_ERRATUM_A007075
165 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
166 #define CONFIG_SYS_FSL_ERRATUM_A006261
167 #define CONFIG_SYS_FSL_ERRATUM_A004477
168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
169 #define CONFIG_ESDHC_HC_BLK_ADDR
171 /* P1011 is single core version of P1020 */
172 #elif defined(CONFIG_ARCH_P1011)
173 #define CONFIG_MAX_CPUS 1
174 #define CONFIG_SYS_FSL_NUM_LAWS 12
175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 #define CONFIG_SYS_FSL_ERRATUM_A004508
184 #define CONFIG_SYS_FSL_ERRATUM_A005125
186 #elif defined(CONFIG_ARCH_P1020)
187 #define CONFIG_MAX_CPUS 2
188 #define CONFIG_SYS_FSL_NUM_LAWS 12
189 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
190 #define CONFIG_TSECV2
191 #define CONFIG_FSL_PCIE_DISABLE_ASPM
192 #define CONFIG_SYS_FSL_SEC_COMPAT 2
193 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
194 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
196 #define CONFIG_SYS_FSL_ERRATUM_A004508
197 #define CONFIG_SYS_FSL_ERRATUM_A005125
198 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
199 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
202 #elif defined(CONFIG_P1021)
203 #define CONFIG_MAX_CPUS 2
204 #define CONFIG_SYS_FSL_NUM_LAWS 12
205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
206 #define CONFIG_TSECV2
207 #define CONFIG_FSL_PCIE_DISABLE_ASPM
208 #define CONFIG_SYS_FSL_SEC_COMPAT 2
209 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
210 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
212 #define QE_MURAM_SIZE 0x6000UL
213 #define MAX_QE_RISC 1
214 #define QE_NUM_OF_SNUM 28
215 #define CONFIG_SYS_FSL_ERRATUM_A004508
216 #define CONFIG_SYS_FSL_ERRATUM_A005125
217 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
219 #elif defined(CONFIG_ARCH_P1022)
220 #define CONFIG_MAX_CPUS 2
221 #define CONFIG_SYS_FSL_NUM_LAWS 12
222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
223 #define CONFIG_TSECV2
224 #define CONFIG_SYS_FSL_SEC_COMPAT 2
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
229 #define CONFIG_FSL_SATA_ERRATUM_A001
230 #define CONFIG_SYS_FSL_ERRATUM_A004508
231 #define CONFIG_SYS_FSL_ERRATUM_A005125
232 #define CONFIG_SYS_FSL_ERRATUM_A004477
234 #elif defined(CONFIG_ARCH_P1023)
235 #define CONFIG_MAX_CPUS 2
236 #define CONFIG_SYS_FSL_NUM_LAWS 12
237 #define CONFIG_SYS_FSL_SEC_COMPAT 4
238 #define CONFIG_SYS_NUM_FMAN 1
239 #define CONFIG_SYS_NUM_FM1_DTSEC 2
240 #define CONFIG_NUM_DDR_CONTROLLERS 1
241 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
242 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
243 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
244 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
245 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
247 #define CONFIG_SYS_FSL_ERRATUM_A004508
248 #define CONFIG_SYS_FSL_ERRATUM_A005125
249 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
250 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
252 /* P1024 is lower end variant of P1020 */
253 #elif defined(CONFIG_P1024)
254 #define CONFIG_MAX_CPUS 2
255 #define CONFIG_SYS_FSL_NUM_LAWS 12
256 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
257 #define CONFIG_TSECV2
258 #define CONFIG_FSL_PCIE_DISABLE_ASPM
259 #define CONFIG_SYS_FSL_SEC_COMPAT 2
260 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
262 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
263 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
264 #define CONFIG_SYS_FSL_ERRATUM_A004508
265 #define CONFIG_SYS_FSL_ERRATUM_A005125
267 /* P1025 is lower end variant of P1021 */
268 #elif defined(CONFIG_P1025)
269 #define CONFIG_MAX_CPUS 2
270 #define CONFIG_SYS_FSL_NUM_LAWS 12
271 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
272 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
273 #define CONFIG_TSECV2
274 #define CONFIG_FSL_PCIE_DISABLE_ASPM
275 #define CONFIG_SYS_FSL_SEC_COMPAT 2
276 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
277 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
279 #define QE_MURAM_SIZE 0x6000UL
280 #define MAX_QE_RISC 1
281 #define QE_NUM_OF_SNUM 28
282 #define CONFIG_SYS_FSL_ERRATUM_A004508
283 #define CONFIG_SYS_FSL_ERRATUM_A005125
285 /* P2010 is single core version of P2020 */
286 #elif defined(CONFIG_P2010)
287 #define CONFIG_MAX_CPUS 1
288 #define CONFIG_SYS_FSL_NUM_LAWS 12
289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
290 #define CONFIG_SYS_FSL_SEC_COMPAT 2
291 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
293 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
295 #define CONFIG_SYS_FSL_ERRATUM_A004508
296 #define CONFIG_SYS_FSL_ERRATUM_A005125
298 #elif defined(CONFIG_P2020)
299 #define CONFIG_MAX_CPUS 2
300 #define CONFIG_SYS_FSL_NUM_LAWS 12
301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
302 #define CONFIG_SYS_FSL_SEC_COMPAT 2
303 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
304 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
305 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
306 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
307 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
308 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
309 #define CONFIG_SYS_FSL_RMU
310 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
311 #define CONFIG_SYS_FSL_ERRATUM_A004508
312 #define CONFIG_SYS_FSL_ERRATUM_A005125
313 #define CONFIG_SYS_FSL_ERRATUM_A004477
314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
316 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
317 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
318 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
319 #define CONFIG_MAX_CPUS 4
320 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
321 #define CONFIG_SYS_FSL_NUM_LAWS 32
322 #define CONFIG_SYS_FSL_SEC_COMPAT 4
323 #define CONFIG_SYS_NUM_FMAN 1
324 #define CONFIG_SYS_NUM_FM1_DTSEC 5
325 #define CONFIG_SYS_NUM_FM1_10GEC 1
326 #define CONFIG_NUM_DDR_CONTROLLERS 1
327 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
328 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
329 #define CONFIG_SYS_FSL_TBCLK_DIV 32
330 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
331 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
332 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
333 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
334 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
336 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
337 #define CONFIG_SYS_FSL_ERRATUM_USB14
338 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
339 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
340 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
341 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
342 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
343 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
344 #define CONFIG_SYS_FSL_ERRATUM_A004510
345 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
346 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
347 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
348 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
349 #define CONFIG_SYS_FSL_ERRATUM_A004849
350 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
351 #define CONFIG_SYS_FSL_ERRATUM_A006261
352 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
354 #elif defined(CONFIG_PPC_P3041)
355 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
356 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
357 #define CONFIG_MAX_CPUS 4
358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
359 #define CONFIG_SYS_FSL_NUM_LAWS 32
360 #define CONFIG_SYS_FSL_SEC_COMPAT 4
361 #define CONFIG_SYS_NUM_FMAN 1
362 #define CONFIG_SYS_NUM_FM1_DTSEC 5
363 #define CONFIG_SYS_NUM_FM1_10GEC 1
364 #define CONFIG_NUM_DDR_CONTROLLERS 1
365 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
366 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
367 #define CONFIG_SYS_FSL_TBCLK_DIV 32
368 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
369 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
370 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
371 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
372 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
373 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
375 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
376 #define CONFIG_SYS_FSL_ERRATUM_USB14
377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
383 #define CONFIG_SYS_FSL_ERRATUM_A004510
384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
386 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
388 #define CONFIG_SYS_FSL_ERRATUM_A004849
389 #define CONFIG_SYS_FSL_ERRATUM_A005812
390 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
391 #define CONFIG_SYS_FSL_ERRATUM_A006261
392 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
394 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
395 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
396 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
397 #define CONFIG_MAX_CPUS 8
398 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
399 #define CONFIG_SYS_FSL_NUM_LAWS 32
400 #define CONFIG_SYS_FSL_SEC_COMPAT 4
401 #define CONFIG_SYS_NUM_FMAN 2
402 #define CONFIG_SYS_NUM_FM1_DTSEC 4
403 #define CONFIG_SYS_NUM_FM2_DTSEC 4
404 #define CONFIG_SYS_NUM_FM1_10GEC 1
405 #define CONFIG_SYS_NUM_FM2_10GEC 1
406 #define CONFIG_NUM_DDR_CONTROLLERS 2
407 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
408 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
409 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
410 #define CONFIG_SYS_FSL_TBCLK_DIV 16
411 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
412 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
413 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
414 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
415 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
416 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
417 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
418 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
419 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
420 #define CONFIG_SYS_P4080_ERRATUM_CPU22
421 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
422 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
423 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
424 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
425 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
426 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
427 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
428 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
429 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
430 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
431 #define CONFIG_SYS_FSL_RMU
432 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
433 #define CONFIG_SYS_FSL_ERRATUM_A004510
434 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
435 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
436 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
437 #define CONFIG_SYS_FSL_ERRATUM_A004849
438 #define CONFIG_SYS_FSL_ERRATUM_A004580
439 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
440 #define CONFIG_SYS_FSL_ERRATUM_A005812
441 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
442 #define CONFIG_SYS_FSL_ERRATUM_A007075
443 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
445 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
446 #define CONFIG_SYS_PPC64 /* 64-bit core */
447 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
448 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
449 #define CONFIG_MAX_CPUS 2
450 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
451 #define CONFIG_SYS_FSL_NUM_LAWS 32
452 #define CONFIG_SYS_FSL_SEC_COMPAT 4
453 #define CONFIG_SYS_NUM_FMAN 1
454 #define CONFIG_SYS_NUM_FM1_DTSEC 5
455 #define CONFIG_SYS_NUM_FM1_10GEC 1
456 #define CONFIG_NUM_DDR_CONTROLLERS 2
457 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
458 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
459 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
460 #define CONFIG_SYS_FSL_TBCLK_DIV 32
461 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
462 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
463 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
464 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
465 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
466 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
467 #define CONFIG_SYS_FSL_ERRATUM_USB14
468 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
469 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
470 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
471 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
472 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
473 #define CONFIG_SYS_FSL_ERRATUM_A004510
474 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
475 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
476 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
477 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
478 #define CONFIG_SYS_FSL_ERRATUM_A006261
479 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
481 #elif defined(CONFIG_PPC_P5040)
482 #define CONFIG_SYS_PPC64
483 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
484 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
485 #define CONFIG_MAX_CPUS 4
486 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
487 #define CONFIG_SYS_FSL_NUM_LAWS 32
488 #define CONFIG_SYS_FSL_SEC_COMPAT 4
489 #define CONFIG_SYS_NUM_FMAN 2
490 #define CONFIG_SYS_NUM_FM1_DTSEC 5
491 #define CONFIG_SYS_NUM_FM1_10GEC 1
492 #define CONFIG_SYS_NUM_FM2_DTSEC 5
493 #define CONFIG_SYS_NUM_FM2_10GEC 1
494 #define CONFIG_NUM_DDR_CONTROLLERS 2
495 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
496 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
497 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
498 #define CONFIG_SYS_FSL_TBCLK_DIV 16
499 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
500 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
501 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
502 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
503 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
504 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
505 #define CONFIG_SYS_FSL_ERRATUM_USB14
506 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
507 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
508 #define CONFIG_SYS_FSL_ERRATUM_A004699
509 #define CONFIG_SYS_FSL_ERRATUM_A004510
510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
511 #define CONFIG_SYS_FSL_ERRATUM_A006261
512 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
513 #define CONFIG_SYS_FSL_ERRATUM_A005812
515 #elif defined(CONFIG_ARCH_BSC9131)
516 #define CONFIG_MAX_CPUS 1
517 #define CONFIG_FSL_SDHC_V2_3
518 #define CONFIG_SYS_FSL_NUM_LAWS 12
519 #define CONFIG_TSECV2
520 #define CONFIG_SYS_FSL_SEC_COMPAT 4
521 #define CONFIG_NUM_DDR_CONTROLLERS 1
522 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
523 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
524 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
525 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
526 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
527 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
528 #define CONFIG_NAND_FSL_IFC
529 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
530 #define CONFIG_SYS_FSL_ERRATUM_A005125
531 #define CONFIG_SYS_FSL_ERRATUM_A004477
532 #define CONFIG_ESDHC_HC_BLK_ADDR
534 #elif defined(CONFIG_ARCH_BSC9132)
535 #define CONFIG_MAX_CPUS 2
536 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
537 #define CONFIG_FSL_SDHC_V2_3
538 #define CONFIG_SYS_FSL_NUM_LAWS 12
539 #define CONFIG_TSECV2
540 #define CONFIG_SYS_FSL_SEC_COMPAT 4
541 #define CONFIG_NUM_DDR_CONTROLLERS 2
542 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
543 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
544 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
545 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
546 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
547 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
548 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
549 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
550 #define CONFIG_NAND_FSL_IFC
551 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
552 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
553 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
554 #define CONFIG_SYS_FSL_ERRATUM_A005125
555 #define CONFIG_SYS_FSL_ERRATUM_A005434
556 #define CONFIG_SYS_FSL_ERRATUM_A004477
557 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
558 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
559 #define CONFIG_ESDHC_HC_BLK_ADDR
561 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
562 defined(CONFIG_PPC_T4080)
564 #define CONFIG_SYS_PPC64 /* 64-bit core */
565 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
566 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
567 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
568 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
569 #ifdef CONFIG_PPC_T4240
570 #define CONFIG_MAX_CPUS 12
571 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
572 #define CONFIG_SYS_NUM_FM1_DTSEC 8
573 #define CONFIG_SYS_NUM_FM1_10GEC 2
574 #define CONFIG_SYS_NUM_FM2_DTSEC 8
575 #define CONFIG_SYS_NUM_FM2_10GEC 2
576 #define CONFIG_NUM_DDR_CONTROLLERS 3
577 #define CONFIG_SYS_FSL_ERRATUM_A006261
579 #define CONFIG_SYS_NUM_FM1_DTSEC 6
580 #define CONFIG_SYS_NUM_FM1_10GEC 1
581 #define CONFIG_SYS_NUM_FM2_DTSEC 8
582 #define CONFIG_SYS_NUM_FM2_10GEC 1
583 #define CONFIG_NUM_DDR_CONTROLLERS 2
584 #if defined(CONFIG_PPC_T4160)
585 #define CONFIG_MAX_CPUS 8
586 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
587 #elif defined(CONFIG_PPC_T4080)
588 #define CONFIG_MAX_CPUS 4
589 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
592 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
593 #define CONFIG_SYS_FSL_NUM_LAWS 32
594 #define CONFIG_SYS_FSL_SRDS_1
595 #define CONFIG_SYS_FSL_SRDS_2
596 #define CONFIG_SYS_FSL_SRDS_3
597 #define CONFIG_SYS_FSL_SRDS_4
598 #define CONFIG_SYS_FSL_SEC_COMPAT 4
599 #define CONFIG_SYS_NUM_FMAN 2
600 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
601 #define CONFIG_SYS_PME_CLK 0
602 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
603 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
604 #define CONFIG_SYS_FMAN_V3
605 #define CONFIG_SYS_FM1_CLK 3
606 #define CONFIG_SYS_FM2_CLK 3
607 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
608 #define CONFIG_SYS_FSL_TBCLK_DIV 16
609 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
610 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
611 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
612 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
613 #define CONFIG_SYS_FSL_SRIO_LIODN
614 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
615 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
616 #define CONFIG_SYS_FSL_ERRATUM_A004468
617 #define CONFIG_SYS_FSL_ERRATUM_A_004934
618 #define CONFIG_SYS_FSL_ERRATUM_A005871
619 #define CONFIG_SYS_FSL_ERRATUM_A006379
620 #define CONFIG_SYS_FSL_ERRATUM_A007186
621 #define CONFIG_SYS_FSL_ERRATUM_A006593
622 #define CONFIG_SYS_FSL_ERRATUM_A007798
623 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
624 #define CONFIG_SYS_FSL_SFP_VER_3_0
625 #define CONFIG_SYS_FSL_PCI_VER_3_X
627 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
629 #define CONFIG_SYS_PPC64 /* 64-bit core */
630 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
631 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
632 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
633 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
634 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
635 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
636 #define CONFIG_SYS_FSL_NUM_LAWS 32
637 #define CONFIG_SYS_FSL_SRDS_1
638 #define CONFIG_SYS_FSL_SRDS_2
639 #define CONFIG_SYS_MAPLE
640 #define CONFIG_SYS_CPRI
641 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
642 #define CONFIG_SYS_FSL_SEC_COMPAT 4
643 #define CONFIG_SYS_NUM_FMAN 1
644 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
645 #define CONFIG_SYS_FM1_CLK 0
646 #define CONFIG_SYS_CPRI_CLK 3
647 #define CONFIG_SYS_ULB_CLK 4
648 #define CONFIG_SYS_ETVPE_CLK 1
649 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
650 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
651 #define CONFIG_SYS_FMAN_V3
652 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
653 #define CONFIG_SYS_FSL_TBCLK_DIV 16
654 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
655 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
656 #define CONFIG_SYS_FSL_ERRATUM_A_004934
657 #define CONFIG_SYS_FSL_ERRATUM_A005871
658 #define CONFIG_SYS_FSL_ERRATUM_A006379
659 #define CONFIG_SYS_FSL_ERRATUM_A007186
660 #define CONFIG_SYS_FSL_ERRATUM_A006593
661 #define CONFIG_SYS_FSL_ERRATUM_A007075
662 #define CONFIG_SYS_FSL_ERRATUM_A006475
663 #define CONFIG_SYS_FSL_ERRATUM_A006384
664 #define CONFIG_SYS_FSL_ERRATUM_A007212
665 #define CONFIG_SYS_FSL_ERRATUM_A004477
666 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
667 #define CONFIG_SYS_FSL_SFP_VER_3_0
669 #ifdef CONFIG_PPC_B4860
670 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
671 #define CONFIG_MAX_CPUS 4
672 #define CONFIG_MAX_DSP_CPUS 12
673 #define CONFIG_NUM_DSP_CPUS 6
674 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
675 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
676 #define CONFIG_SYS_NUM_FM1_DTSEC 6
677 #define CONFIG_SYS_NUM_FM1_10GEC 2
678 #define CONFIG_NUM_DDR_CONTROLLERS 2
679 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
680 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
681 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
682 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
683 #define CONFIG_SYS_FSL_SRIO_LIODN
685 #define CONFIG_MAX_CPUS 2
686 #define CONFIG_MAX_DSP_CPUS 2
687 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
688 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
689 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
690 #define CONFIG_SYS_NUM_FM1_DTSEC 4
691 #define CONFIG_SYS_NUM_FM1_10GEC 0
692 #define CONFIG_NUM_DDR_CONTROLLERS 1
695 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
696 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
698 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
699 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
700 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
701 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
702 #ifdef CONFIG_SYS_FSL_DDR4
703 #define CONFIG_SYS_FSL_DDRC_GEN4
705 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
706 #define CONFIG_MAX_CPUS 4
707 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
708 #define CONFIG_MAX_CPUS 2
710 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
711 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
712 #define CONFIG_SYS_FSL_NUM_LAWS 16
713 #define CONFIG_SYS_FSL_SRDS_1
714 #define CONFIG_SYS_FSL_SEC_COMPAT 5
715 #define CONFIG_SYS_NUM_FMAN 1
716 #define CONFIG_SYS_NUM_FM1_DTSEC 5
717 #define CONFIG_NUM_DDR_CONTROLLERS 1
718 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
719 #define CONFIG_PME_PLAT_CLK_DIV 2
720 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
721 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
722 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
723 #define CONFIG_SYS_FSL_ERRATUM_A008044
724 #define CONFIG_SYS_FMAN_V3
725 #define CONFIG_FM_PLAT_CLK_DIV 1
726 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
727 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
728 per rcw field value */
729 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
730 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
731 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
732 #define CONFIG_SYS_FSL_TBCLK_DIV 16
733 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
734 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
735 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
736 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
737 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
738 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
739 #define QE_MURAM_SIZE 0x6000UL
740 #define MAX_QE_RISC 1
741 #define QE_NUM_OF_SNUM 28
742 #define CONFIG_SYS_FSL_SFP_VER_3_0
743 #define CONFIG_SYS_FSL_ERRATUM_A008378
744 #define CONFIG_SYS_FSL_ERRATUM_A009663
746 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
747 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
749 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
750 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
751 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
752 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
753 #define CONFIG_SYS_FMAN_V3
754 #ifdef CONFIG_SYS_FSL_DDR4
755 #define CONFIG_SYS_FSL_DDRC_GEN4
757 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
758 #define CONFIG_MAX_CPUS 2
759 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
760 #define CONFIG_MAX_CPUS 1
762 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
763 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
764 #define CONFIG_SYS_FSL_NUM_LAWS 16
765 #define CONFIG_SYS_FSL_SRDS_1
766 #define CONFIG_SYS_FSL_SEC_COMPAT 5
767 #define CONFIG_SYS_NUM_FMAN 1
768 #define CONFIG_SYS_NUM_FM1_DTSEC 4
769 #define CONFIG_SYS_NUM_FM1_10GEC 1
770 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
771 #define CONFIG_NUM_DDR_CONTROLLERS 1
772 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
773 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
774 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
775 #define CONFIG_SYS_FM1_CLK 0
776 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
777 per rcw field value */
778 #define CONFIG_QBMAN_CLK_DIV 1
779 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
780 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
781 #define CONFIG_SYS_FSL_TBCLK_DIV 16
782 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
783 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
784 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
785 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
786 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
787 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
788 #define QE_MURAM_SIZE 0x6000UL
789 #define MAX_QE_RISC 1
790 #define QE_NUM_OF_SNUM 28
791 #define CONFIG_SYS_FSL_SFP_VER_3_0
792 #define CONFIG_SYS_FSL_ERRATUM_A008378
793 #define CONFIG_SYS_FSL_ERRATUM_A009663
795 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
797 #define CONFIG_SYS_PPC64 /* 64-bit core */
798 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
799 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
800 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
801 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
802 #define CONFIG_SYS_FSL_QMAN_V3
803 #define CONFIG_MAX_CPUS 4
804 #define CONFIG_SYS_FSL_NUM_LAWS 32
805 #define CONFIG_SYS_FSL_SEC_COMPAT 4
806 #define CONFIG_SYS_NUM_FMAN 1
807 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
808 #define CONFIG_SYS_FSL_SRDS_1
809 #define CONFIG_SYS_FSL_PCI_VER_3_X
810 #if defined(CONFIG_PPC_T2080)
811 #define CONFIG_SYS_NUM_FM1_DTSEC 8
812 #define CONFIG_SYS_NUM_FM1_10GEC 4
813 #define CONFIG_SYS_FSL_SRDS_2
814 #define CONFIG_SYS_FSL_SRIO_LIODN
815 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
816 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
817 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
818 #elif defined(CONFIG_PPC_T2081)
819 #define CONFIG_SYS_NUM_FM1_DTSEC 6
820 #define CONFIG_SYS_NUM_FM1_10GEC 2
822 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
823 #define CONFIG_NUM_DDR_CONTROLLERS 1
824 #define CONFIG_PME_PLAT_CLK_DIV 1
825 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
826 #define CONFIG_SYS_FM1_CLK 0
827 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
828 per rcw field value */
829 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
830 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
831 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
832 #define CONFIG_SYS_FMAN_V3
833 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
834 #define CONFIG_SYS_FSL_TBCLK_DIV 16
835 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
836 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
837 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
838 #define CONFIG_SYS_FSL_ERRATUM_A007212
839 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
840 #define CONFIG_SYS_FSL_SFP_VER_3_0
841 #define CONFIG_SYS_FSL_ISBC_VER 2
842 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
843 #define CONFIG_SYS_FSL_ERRATUM_A006593
844 #define CONFIG_SYS_FSL_ERRATUM_A007186
845 #define CONFIG_SYS_FSL_ERRATUM_A006379
846 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
847 #define CONFIG_SYS_FSL_SFP_VER_3_0
850 #elif defined(CONFIG_ARCH_C29X)
851 #define CONFIG_MAX_CPUS 1
852 #define CONFIG_FSL_SDHC_V2_3
853 #define CONFIG_SYS_FSL_NUM_LAWS 12
854 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
855 #define CONFIG_TSECV2_1
856 #define CONFIG_SYS_FSL_SEC_COMPAT 6
857 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
858 #define CONFIG_NUM_DDR_CONTROLLERS 1
859 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
860 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
861 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
862 #define CONFIG_SYS_FSL_ERRATUM_A005125
863 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
864 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
866 #elif defined(CONFIG_QEMU_E500)
867 #define CONFIG_MAX_CPUS 1
868 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
871 #error Processor type not defined for this platform
874 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
875 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
879 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
881 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
884 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
885 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
886 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
887 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
888 #define CONFIG_SYS_FSL_DDRC_GEN3
891 #if !defined(CONFIG_ARCH_C29X)
892 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
895 #endif /* _ASM_MPC85xx_CONFIG_H_ */