2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
30 /* Number of TLB CAM entries we have on FSL Book-E chips */
31 #if defined(CONFIG_E500MC)
32 #define CONFIG_SYS_NUM_TLBCAMS 64
33 #elif defined(CONFIG_E500)
34 #define CONFIG_SYS_NUM_TLBCAMS 16
37 #if defined(CONFIG_MPC8536)
38 #define CONFIG_MAX_CPUS 1
39 #define CONFIG_SYS_FSL_NUM_LAWS 12
40 #define CONFIG_SYS_FSL_SEC_COMPAT 2
41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
48 #elif defined(CONFIG_MPC8541)
49 #define CONFIG_MAX_CPUS 1
50 #define CONFIG_SYS_FSL_NUM_LAWS 8
51 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
54 #elif defined(CONFIG_MPC8544)
55 #define CONFIG_MAX_CPUS 1
56 #define CONFIG_SYS_FSL_NUM_LAWS 10
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_MPC8548)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_SEC_COMPAT 2
64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
69 #elif defined(CONFIG_MPC8555)
70 #define CONFIG_MAX_CPUS 1
71 #define CONFIG_SYS_FSL_NUM_LAWS 8
72 #define CONFIG_SYS_FSL_SEC_COMPAT 2
73 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
75 #elif defined(CONFIG_MPC8560)
76 #define CONFIG_MAX_CPUS 1
77 #define CONFIG_SYS_FSL_NUM_LAWS 8
78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
80 #elif defined(CONFIG_MPC8568)
81 #define CONFIG_MAX_CPUS 1
82 #define CONFIG_SYS_FSL_NUM_LAWS 10
83 #define CONFIG_SYS_FSL_SEC_COMPAT 2
84 #define QE_MURAM_SIZE 0x10000UL
86 #define QE_NUM_OF_SNUM 28
87 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
89 #elif defined(CONFIG_MPC8569)
90 #define CONFIG_MAX_CPUS 1
91 #define CONFIG_SYS_FSL_NUM_LAWS 10
92 #define CONFIG_SYS_FSL_SEC_COMPAT 2
93 #define QE_MURAM_SIZE 0x20000UL
95 #define QE_NUM_OF_SNUM 46
96 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
98 #elif defined(CONFIG_MPC8572)
99 #define CONFIG_MAX_CPUS 2
100 #define CONFIG_SYS_FSL_NUM_LAWS 12
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
103 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
104 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
106 #elif defined(CONFIG_P1010)
107 #define CONFIG_MAX_CPUS 1
108 #define CONFIG_FSL_SDHC_V2_3
109 #define CONFIG_SYS_FSL_NUM_LAWS 12
110 #define CONFIG_TSECV2
111 #define CONFIG_SYS_FSL_SEC_COMPAT 4
112 #define CONFIG_FSL_SATA_V2
113 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
114 #define CONFIG_NUM_DDR_CONTROLLERS 1
115 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
116 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
117 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
118 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
119 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
120 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
122 /* P1011 is single core version of P1020 */
123 #elif defined(CONFIG_P1011)
124 #define CONFIG_MAX_CPUS 1
125 #define CONFIG_SYS_FSL_NUM_LAWS 12
126 #define CONFIG_TSECV2
127 #define CONFIG_FSL_PCIE_DISABLE_ASPM
128 #define CONFIG_SYS_FSL_SEC_COMPAT 2
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
131 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
133 /* P1012 is single core version of P1021 */
134 #elif defined(CONFIG_P1012)
135 #define CONFIG_MAX_CPUS 1
136 #define CONFIG_SYS_FSL_NUM_LAWS 12
137 #define CONFIG_TSECV2
138 #define CONFIG_FSL_PCIE_DISABLE_ASPM
139 #define CONFIG_SYS_FSL_SEC_COMPAT 2
140 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
141 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
142 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
143 #define QE_MURAM_SIZE 0x6000UL
144 #define MAX_QE_RISC 1
145 #define QE_NUM_OF_SNUM 28
147 /* P1013 is single core version of P1022 */
148 #elif defined(CONFIG_P1013)
149 #define CONFIG_MAX_CPUS 1
150 #define CONFIG_SYS_FSL_NUM_LAWS 12
151 #define CONFIG_TSECV2
152 #define CONFIG_SYS_FSL_SEC_COMPAT 2
153 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
154 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
155 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
156 #define CONFIG_FSL_SATA_ERRATUM_A001
158 #elif defined(CONFIG_P1014)
159 #define CONFIG_MAX_CPUS 1
160 #define CONFIG_FSL_SDHC_V2_3
161 #define CONFIG_SYS_FSL_NUM_LAWS 12
162 #define CONFIG_TSECV2
163 #define CONFIG_SYS_FSL_SEC_COMPAT 4
164 #define CONFIG_FSL_SATA_V2
165 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
166 #define CONFIG_NUM_DDR_CONTROLLERS 1
167 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
168 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
169 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
170 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
171 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
173 /* P1015 is single core version of P1024 */
174 #elif defined(CONFIG_P1015)
175 #define CONFIG_MAX_CPUS 1
176 #define CONFIG_SYS_FSL_NUM_LAWS 12
177 #define CONFIG_TSECV2
178 #define CONFIG_FSL_PCIE_DISABLE_ASPM
179 #define CONFIG_SYS_FSL_SEC_COMPAT 2
180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
184 /* P1016 is single core version of P1025 */
185 #elif defined(CONFIG_P1016)
186 #define CONFIG_MAX_CPUS 1
187 #define CONFIG_SYS_FSL_NUM_LAWS 12
188 #define CONFIG_TSECV2
189 #define CONFIG_FSL_PCIE_DISABLE_ASPM
190 #define CONFIG_SYS_FSL_SEC_COMPAT 2
191 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
192 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
193 #define QE_MURAM_SIZE 0x6000UL
194 #define MAX_QE_RISC 1
195 #define QE_NUM_OF_SNUM 28
196 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
198 /* P1017 is single core version of P1023 */
199 #elif defined(CONFIG_P1017)
200 #define CONFIG_MAX_CPUS 1
201 #define CONFIG_SYS_FSL_NUM_LAWS 12
202 #define CONFIG_SYS_FSL_SEC_COMPAT 4
203 #define CONFIG_SYS_NUM_FMAN 1
204 #define CONFIG_SYS_NUM_FM1_DTSEC 2
205 #define CONFIG_NUM_DDR_CONTROLLERS 1
206 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
207 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
208 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
209 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
210 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
212 #elif defined(CONFIG_P1020)
213 #define CONFIG_MAX_CPUS 2
214 #define CONFIG_SYS_FSL_NUM_LAWS 12
215 #define CONFIG_TSECV2
216 #define CONFIG_FSL_PCIE_DISABLE_ASPM
217 #define CONFIG_SYS_FSL_SEC_COMPAT 2
218 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
219 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
220 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
222 #elif defined(CONFIG_P1021)
223 #define CONFIG_MAX_CPUS 2
224 #define CONFIG_SYS_FSL_NUM_LAWS 12
225 #define CONFIG_TSECV2
226 #define CONFIG_FSL_PCIE_DISABLE_ASPM
227 #define CONFIG_SYS_FSL_SEC_COMPAT 2
228 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
229 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
230 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
231 #define QE_MURAM_SIZE 0x6000UL
232 #define MAX_QE_RISC 1
233 #define QE_NUM_OF_SNUM 28
235 #elif defined(CONFIG_P1022)
236 #define CONFIG_MAX_CPUS 2
237 #define CONFIG_SYS_FSL_NUM_LAWS 12
238 #define CONFIG_TSECV2
239 #define CONFIG_SYS_FSL_SEC_COMPAT 2
240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
243 #define CONFIG_FSL_SATA_ERRATUM_A001
245 #elif defined(CONFIG_P1023)
246 #define CONFIG_MAX_CPUS 2
247 #define CONFIG_SYS_FSL_NUM_LAWS 12
248 #define CONFIG_SYS_FSL_SEC_COMPAT 4
249 #define CONFIG_SYS_NUM_FMAN 1
250 #define CONFIG_SYS_NUM_FM1_DTSEC 2
251 #define CONFIG_NUM_DDR_CONTROLLERS 1
252 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
253 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
254 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
255 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
256 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
258 /* P1024 is lower end variant of P1020 */
259 #elif defined(CONFIG_P1024)
260 #define CONFIG_MAX_CPUS 2
261 #define CONFIG_SYS_FSL_NUM_LAWS 12
262 #define CONFIG_TSECV2
263 #define CONFIG_FSL_PCIE_DISABLE_ASPM
264 #define CONFIG_SYS_FSL_SEC_COMPAT 2
265 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
266 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
267 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
269 /* P1025 is lower end variant of P1021 */
270 #elif defined(CONFIG_P1025)
271 #define CONFIG_MAX_CPUS 2
272 #define CONFIG_SYS_FSL_NUM_LAWS 12
273 #define CONFIG_TSECV2
274 #define CONFIG_FSL_PCIE_DISABLE_ASPM
275 #define CONFIG_SYS_FSL_SEC_COMPAT 2
276 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
277 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
279 #define QE_MURAM_SIZE 0x6000UL
280 #define MAX_QE_RISC 1
281 #define QE_NUM_OF_SNUM 28
283 /* P2010 is single core version of P2020 */
284 #elif defined(CONFIG_P2010)
285 #define CONFIG_MAX_CPUS 1
286 #define CONFIG_SYS_FSL_NUM_LAWS 12
287 #define CONFIG_SYS_FSL_SEC_COMPAT 2
288 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
289 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
290 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
292 #elif defined(CONFIG_P2020)
293 #define CONFIG_MAX_CPUS 2
294 #define CONFIG_SYS_FSL_NUM_LAWS 12
295 #define CONFIG_SYS_FSL_SEC_COMPAT 2
296 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
298 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
300 #elif defined(CONFIG_PPC_P2040)
301 #define CONFIG_MAX_CPUS 4
302 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
303 #define CONFIG_SYS_FSL_NUM_LAWS 32
304 #define CONFIG_SYS_FSL_SEC_COMPAT 4
305 #define CONFIG_SYS_NUM_FMAN 1
306 #define CONFIG_SYS_NUM_FM1_DTSEC 5
307 #define CONFIG_NUM_DDR_CONTROLLERS 1
308 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
309 #define CONFIG_SYS_FSL_TBCLK_DIV 32
310 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
311 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
312 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
313 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
314 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
315 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
317 #elif defined(CONFIG_PPC_P2041)
318 #define CONFIG_MAX_CPUS 4
319 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
320 #define CONFIG_SYS_FSL_NUM_LAWS 32
321 #define CONFIG_SYS_FSL_SEC_COMPAT 4
322 #define CONFIG_SYS_NUM_FMAN 1
323 #define CONFIG_SYS_NUM_FM1_DTSEC 5
324 #define CONFIG_SYS_NUM_FM1_10GEC 1
325 #define CONFIG_NUM_DDR_CONTROLLERS 1
326 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
327 #define CONFIG_SYS_FSL_TBCLK_DIV 32
328 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
329 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
330 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
331 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
332 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
333 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
335 #elif defined(CONFIG_PPC_P3041)
336 #define CONFIG_MAX_CPUS 4
337 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
338 #define CONFIG_SYS_FSL_NUM_LAWS 32
339 #define CONFIG_SYS_FSL_SEC_COMPAT 4
340 #define CONFIG_SYS_NUM_FMAN 1
341 #define CONFIG_SYS_NUM_FM1_DTSEC 5
342 #define CONFIG_SYS_NUM_FM1_10GEC 1
343 #define CONFIG_NUM_DDR_CONTROLLERS 1
344 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
345 #define CONFIG_SYS_FSL_TBCLK_DIV 32
346 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
347 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
348 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
349 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
350 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
351 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
353 #elif defined(CONFIG_PPC_P3060)
354 #define CONFIG_MAX_CPUS 8
355 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
356 #define CONFIG_SYS_FSL_NUM_LAWS 32
357 #define CONFIG_SYS_FSL_SEC_COMPAT 4
358 #define CONFIG_SYS_NUM_FMAN 2
359 #define CONFIG_SYS_NUM_FM1_DTSEC 4
360 #define CONFIG_SYS_NUM_FM2_DTSEC 4
361 #define CONFIG_NUM_DDR_CONTROLLERS 1
362 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
363 #define CONFIG_SYS_FSL_TBCLK_DIV 16
364 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
366 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
368 #elif defined(CONFIG_PPC_P4040)
369 #define CONFIG_MAX_CPUS 4
370 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
371 #define CONFIG_SYS_FSL_NUM_LAWS 32
372 #define CONFIG_SYS_FSL_SEC_COMPAT 4
373 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
374 #define CONFIG_SYS_FSL_TBCLK_DIV 16
375 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
376 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
378 #elif defined(CONFIG_PPC_P4080)
379 #define CONFIG_MAX_CPUS 8
380 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
381 #define CONFIG_SYS_FSL_NUM_LAWS 32
382 #define CONFIG_SYS_FSL_SEC_COMPAT 4
383 #define CONFIG_SYS_NUM_FMAN 2
384 #define CONFIG_SYS_NUM_FM1_DTSEC 4
385 #define CONFIG_SYS_NUM_FM2_DTSEC 4
386 #define CONFIG_SYS_NUM_FM1_10GEC 1
387 #define CONFIG_SYS_NUM_FM2_10GEC 1
388 #define CONFIG_NUM_DDR_CONTROLLERS 2
389 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
390 #define CONFIG_SYS_FSL_TBCLK_DIV 16
391 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
392 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
393 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
394 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
395 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
396 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
397 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
398 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
400 #define CONFIG_SYS_P4080_ERRATUM_CPU22
401 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
402 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
403 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
404 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
406 /* P5010 is single core version of P5020 */
407 #elif defined(CONFIG_PPC_P5010)
408 #define CONFIG_MAX_CPUS 1
409 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
410 #define CONFIG_SYS_FSL_NUM_LAWS 32
411 #define CONFIG_SYS_FSL_SEC_COMPAT 4
412 #define CONFIG_SYS_NUM_FMAN 1
413 #define CONFIG_SYS_NUM_FM1_DTSEC 5
414 #define CONFIG_SYS_NUM_FM1_10GEC 1
415 #define CONFIG_NUM_DDR_CONTROLLERS 1
416 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
417 #define CONFIG_SYS_FSL_TBCLK_DIV 32
418 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
419 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
420 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
421 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
422 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
423 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
425 #elif defined(CONFIG_PPC_P5020)
426 #define CONFIG_MAX_CPUS 2
427 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
428 #define CONFIG_SYS_FSL_NUM_LAWS 32
429 #define CONFIG_SYS_FSL_SEC_COMPAT 4
430 #define CONFIG_SYS_NUM_FMAN 1
431 #define CONFIG_SYS_NUM_FM1_DTSEC 5
432 #define CONFIG_SYS_NUM_FM1_10GEC 1
433 #define CONFIG_NUM_DDR_CONTROLLERS 2
434 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
435 #define CONFIG_SYS_FSL_TBCLK_DIV 32
436 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
437 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
438 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
439 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
440 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
441 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
444 #error Processor type not defined for this platform
447 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
448 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
451 #endif /* _ASM_MPC85xx_CONFIG_H_ */