2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
30 /* Number of TLB CAM entries we have on FSL Book-E chips */
31 #if defined(CONFIG_E500MC)
32 #define CONFIG_SYS_NUM_TLBCAMS 64
33 #elif defined(CONFIG_E500)
34 #define CONFIG_SYS_NUM_TLBCAMS 16
37 #if defined(CONFIG_MPC8536)
38 #define CONFIG_MAX_CPUS 1
39 #define CONFIG_SYS_FSL_NUM_LAWS 12
40 #define CONFIG_SYS_FSL_SEC_COMPAT 2
41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
48 #elif defined(CONFIG_MPC8541)
49 #define CONFIG_MAX_CPUS 1
50 #define CONFIG_SYS_FSL_NUM_LAWS 8
51 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
54 #elif defined(CONFIG_MPC8544)
55 #define CONFIG_MAX_CPUS 1
56 #define CONFIG_SYS_FSL_NUM_LAWS 10
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_MPC8548)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_SEC_COMPAT 2
64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
68 #elif defined(CONFIG_MPC8555)
69 #define CONFIG_MAX_CPUS 1
70 #define CONFIG_SYS_FSL_NUM_LAWS 8
71 #define CONFIG_SYS_FSL_SEC_COMPAT 2
72 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
74 #elif defined(CONFIG_MPC8560)
75 #define CONFIG_MAX_CPUS 1
76 #define CONFIG_SYS_FSL_NUM_LAWS 8
77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
79 #elif defined(CONFIG_MPC8568)
80 #define CONFIG_MAX_CPUS 1
81 #define CONFIG_SYS_FSL_NUM_LAWS 10
82 #define CONFIG_SYS_FSL_SEC_COMPAT 2
83 #define QE_MURAM_SIZE 0x10000UL
85 #define QE_NUM_OF_SNUM 28
86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
88 #elif defined(CONFIG_MPC8569)
89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 10
91 #define CONFIG_SYS_FSL_SEC_COMPAT 2
92 #define QE_MURAM_SIZE 0x20000UL
94 #define QE_NUM_OF_SNUM 46
95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
97 #elif defined(CONFIG_MPC8572)
98 #define CONFIG_MAX_CPUS 2
99 #define CONFIG_SYS_FSL_NUM_LAWS 12
100 #define CONFIG_SYS_FSL_SEC_COMPAT 2
101 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
102 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
103 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
105 #elif defined(CONFIG_P1010)
106 #define CONFIG_MAX_CPUS 1
107 #define CONFIG_FSL_SDHC_V2_3
108 #define CONFIG_SYS_FSL_NUM_LAWS 12
109 #define CONFIG_TSECV2
110 #define CONFIG_SYS_FSL_SEC_COMPAT 4
111 #define CONFIG_FSL_SATA_V2
112 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
113 #define CONFIG_NUM_DDR_CONTROLLERS 1
114 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
115 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
116 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
117 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
118 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
119 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
121 /* P1011 is single core version of P1020 */
122 #elif defined(CONFIG_P1011)
123 #define CONFIG_MAX_CPUS 1
124 #define CONFIG_SYS_FSL_NUM_LAWS 12
125 #define CONFIG_TSECV2
126 #define CONFIG_FSL_PCIE_DISABLE_ASPM
127 #define CONFIG_SYS_FSL_SEC_COMPAT 2
128 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
129 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
130 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
132 /* P1012 is single core version of P1021 */
133 #elif defined(CONFIG_P1012)
134 #define CONFIG_MAX_CPUS 1
135 #define CONFIG_SYS_FSL_NUM_LAWS 12
136 #define CONFIG_TSECV2
137 #define CONFIG_FSL_PCIE_DISABLE_ASPM
138 #define CONFIG_SYS_FSL_SEC_COMPAT 2
139 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
140 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142 #define QE_MURAM_SIZE 0x6000UL
143 #define MAX_QE_RISC 1
144 #define QE_NUM_OF_SNUM 28
146 /* P1013 is single core version of P1022 */
147 #elif defined(CONFIG_P1013)
148 #define CONFIG_MAX_CPUS 1
149 #define CONFIG_SYS_FSL_NUM_LAWS 12
150 #define CONFIG_TSECV2
151 #define CONFIG_SYS_FSL_SEC_COMPAT 2
152 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
153 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
154 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
155 #define CONFIG_FSL_SATA_ERRATUM_A001
157 #elif defined(CONFIG_P1014)
158 #define CONFIG_MAX_CPUS 1
159 #define CONFIG_FSL_SDHC_V2_3
160 #define CONFIG_SYS_FSL_NUM_LAWS 12
161 #define CONFIG_TSECV2
162 #define CONFIG_SYS_FSL_SEC_COMPAT 4
163 #define CONFIG_FSL_SATA_V2
164 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
165 #define CONFIG_NUM_DDR_CONTROLLERS 1
166 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
167 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
168 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
169 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
170 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
172 /* P1015 is single core version of P1024 */
173 #elif defined(CONFIG_P1015)
174 #define CONFIG_MAX_CPUS 1
175 #define CONFIG_SYS_FSL_NUM_LAWS 12
176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 /* P1016 is single core version of P1025 */
184 #elif defined(CONFIG_P1016)
185 #define CONFIG_MAX_CPUS 1
186 #define CONFIG_SYS_FSL_NUM_LAWS 12
187 #define CONFIG_TSECV2
188 #define CONFIG_FSL_PCIE_DISABLE_ASPM
189 #define CONFIG_SYS_FSL_SEC_COMPAT 2
190 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
191 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
192 #define QE_MURAM_SIZE 0x6000UL
193 #define MAX_QE_RISC 1
194 #define QE_NUM_OF_SNUM 28
195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
197 /* P1017 is single core version of P1023 */
198 #elif defined(CONFIG_P1017)
199 #define CONFIG_MAX_CPUS 1
200 #define CONFIG_SYS_FSL_NUM_LAWS 12
201 #define CONFIG_SYS_FSL_SEC_COMPAT 4
202 #define CONFIG_SYS_NUM_FMAN 1
203 #define CONFIG_SYS_NUM_FM1_DTSEC 2
204 #define CONFIG_NUM_DDR_CONTROLLERS 1
205 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
206 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
207 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
208 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
209 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
211 #elif defined(CONFIG_P1020)
212 #define CONFIG_MAX_CPUS 2
213 #define CONFIG_SYS_FSL_NUM_LAWS 12
214 #define CONFIG_TSECV2
215 #define CONFIG_FSL_PCIE_DISABLE_ASPM
216 #define CONFIG_SYS_FSL_SEC_COMPAT 2
217 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
218 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
219 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
221 #elif defined(CONFIG_P1021)
222 #define CONFIG_MAX_CPUS 2
223 #define CONFIG_SYS_FSL_NUM_LAWS 12
224 #define CONFIG_TSECV2
225 #define CONFIG_FSL_PCIE_DISABLE_ASPM
226 #define CONFIG_SYS_FSL_SEC_COMPAT 2
227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
228 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
229 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
230 #define QE_MURAM_SIZE 0x6000UL
231 #define MAX_QE_RISC 1
232 #define QE_NUM_OF_SNUM 28
234 #elif defined(CONFIG_P1022)
235 #define CONFIG_MAX_CPUS 2
236 #define CONFIG_SYS_FSL_NUM_LAWS 12
237 #define CONFIG_TSECV2
238 #define CONFIG_SYS_FSL_SEC_COMPAT 2
239 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
240 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
241 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
242 #define CONFIG_FSL_SATA_ERRATUM_A001
244 #elif defined(CONFIG_P1023)
245 #define CONFIG_MAX_CPUS 2
246 #define CONFIG_SYS_FSL_NUM_LAWS 12
247 #define CONFIG_SYS_FSL_SEC_COMPAT 4
248 #define CONFIG_SYS_NUM_FMAN 1
249 #define CONFIG_SYS_NUM_FM1_DTSEC 2
250 #define CONFIG_NUM_DDR_CONTROLLERS 1
251 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
252 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
253 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
254 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
255 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
257 /* P1024 is lower end variant of P1020 */
258 #elif defined(CONFIG_P1024)
259 #define CONFIG_MAX_CPUS 2
260 #define CONFIG_SYS_FSL_NUM_LAWS 12
261 #define CONFIG_TSECV2
262 #define CONFIG_FSL_PCIE_DISABLE_ASPM
263 #define CONFIG_SYS_FSL_SEC_COMPAT 2
264 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
265 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
266 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
268 /* P1025 is lower end variant of P1021 */
269 #elif defined(CONFIG_P1025)
270 #define CONFIG_MAX_CPUS 2
271 #define CONFIG_SYS_FSL_NUM_LAWS 12
272 #define CONFIG_TSECV2
273 #define CONFIG_FSL_PCIE_DISABLE_ASPM
274 #define CONFIG_SYS_FSL_SEC_COMPAT 2
275 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
276 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
277 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
278 #define QE_MURAM_SIZE 0x6000UL
279 #define MAX_QE_RISC 1
280 #define QE_NUM_OF_SNUM 28
282 /* P2010 is single core version of P2020 */
283 #elif defined(CONFIG_P2010)
284 #define CONFIG_MAX_CPUS 1
285 #define CONFIG_SYS_FSL_NUM_LAWS 12
286 #define CONFIG_SYS_FSL_SEC_COMPAT 2
287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
289 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
291 #elif defined(CONFIG_P2020)
292 #define CONFIG_MAX_CPUS 2
293 #define CONFIG_SYS_FSL_NUM_LAWS 12
294 #define CONFIG_SYS_FSL_SEC_COMPAT 2
295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
299 #elif defined(CONFIG_PPC_P2040)
300 #define CONFIG_MAX_CPUS 4
301 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
302 #define CONFIG_SYS_FSL_NUM_LAWS 32
303 #define CONFIG_SYS_FSL_SEC_COMPAT 4
304 #define CONFIG_SYS_NUM_FMAN 1
305 #define CONFIG_SYS_NUM_FM1_DTSEC 5
306 #define CONFIG_NUM_DDR_CONTROLLERS 1
307 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
308 #define CONFIG_SYS_FSL_TBCLK_DIV 32
309 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
310 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
311 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
312 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
313 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
314 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
316 #elif defined(CONFIG_PPC_P2041)
317 #define CONFIG_MAX_CPUS 4
318 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
319 #define CONFIG_SYS_FSL_NUM_LAWS 32
320 #define CONFIG_SYS_FSL_SEC_COMPAT 4
321 #define CONFIG_SYS_NUM_FMAN 1
322 #define CONFIG_SYS_NUM_FM1_DTSEC 5
323 #define CONFIG_SYS_NUM_FM1_10GEC 1
324 #define CONFIG_NUM_DDR_CONTROLLERS 1
325 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
326 #define CONFIG_SYS_FSL_TBCLK_DIV 32
327 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
328 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
329 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
330 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
331 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
332 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
334 #elif defined(CONFIG_PPC_P3041)
335 #define CONFIG_MAX_CPUS 4
336 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
337 #define CONFIG_SYS_FSL_NUM_LAWS 32
338 #define CONFIG_SYS_FSL_SEC_COMPAT 4
339 #define CONFIG_SYS_NUM_FMAN 1
340 #define CONFIG_SYS_NUM_FM1_DTSEC 5
341 #define CONFIG_SYS_NUM_FM1_10GEC 1
342 #define CONFIG_NUM_DDR_CONTROLLERS 1
343 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
344 #define CONFIG_SYS_FSL_TBCLK_DIV 32
345 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
346 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
347 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
348 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
349 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
350 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
352 #elif defined(CONFIG_PPC_P3060)
353 #define CONFIG_MAX_CPUS 8
354 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
355 #define CONFIG_SYS_FSL_NUM_LAWS 32
356 #define CONFIG_SYS_FSL_SEC_COMPAT 4
357 #define CONFIG_SYS_NUM_FMAN 2
358 #define CONFIG_SYS_NUM_FM1_DTSEC 4
359 #define CONFIG_SYS_NUM_FM2_DTSEC 4
360 #define CONFIG_NUM_DDR_CONTROLLERS 1
361 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
362 #define CONFIG_SYS_FSL_TBCLK_DIV 16
363 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
364 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
365 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
367 #elif defined(CONFIG_PPC_P4040)
368 #define CONFIG_MAX_CPUS 4
369 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
370 #define CONFIG_SYS_FSL_NUM_LAWS 32
371 #define CONFIG_SYS_FSL_SEC_COMPAT 4
372 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
373 #define CONFIG_SYS_FSL_TBCLK_DIV 16
374 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
375 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
377 #elif defined(CONFIG_PPC_P4080)
378 #define CONFIG_MAX_CPUS 8
379 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
380 #define CONFIG_SYS_FSL_NUM_LAWS 32
381 #define CONFIG_SYS_FSL_SEC_COMPAT 4
382 #define CONFIG_SYS_NUM_FMAN 2
383 #define CONFIG_SYS_NUM_FM1_DTSEC 4
384 #define CONFIG_SYS_NUM_FM2_DTSEC 4
385 #define CONFIG_SYS_NUM_FM1_10GEC 1
386 #define CONFIG_SYS_NUM_FM2_10GEC 1
387 #define CONFIG_NUM_DDR_CONTROLLERS 2
388 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
389 #define CONFIG_SYS_FSL_TBCLK_DIV 16
390 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
391 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
392 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
393 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
394 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
395 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
396 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
397 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
398 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
399 #define CONFIG_SYS_P4080_ERRATUM_CPU22
400 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
401 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
402 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
403 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
405 /* P5010 is single core version of P5020 */
406 #elif defined(CONFIG_PPC_P5010)
407 #define CONFIG_MAX_CPUS 1
408 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
409 #define CONFIG_SYS_FSL_NUM_LAWS 32
410 #define CONFIG_SYS_FSL_SEC_COMPAT 4
411 #define CONFIG_SYS_NUM_FMAN 1
412 #define CONFIG_SYS_NUM_FM1_DTSEC 5
413 #define CONFIG_SYS_NUM_FM1_10GEC 1
414 #define CONFIG_NUM_DDR_CONTROLLERS 1
415 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
416 #define CONFIG_SYS_FSL_TBCLK_DIV 32
417 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
418 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
419 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
420 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
421 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
422 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
424 #elif defined(CONFIG_PPC_P5020)
425 #define CONFIG_MAX_CPUS 2
426 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
427 #define CONFIG_SYS_FSL_NUM_LAWS 32
428 #define CONFIG_SYS_FSL_SEC_COMPAT 4
429 #define CONFIG_SYS_NUM_FMAN 1
430 #define CONFIG_SYS_NUM_FM1_DTSEC 5
431 #define CONFIG_SYS_NUM_FM1_10GEC 1
432 #define CONFIG_NUM_DDR_CONTROLLERS 2
433 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
434 #define CONFIG_SYS_FSL_TBCLK_DIV 32
435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
436 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
437 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
438 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
439 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
440 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
443 #error Processor type not defined for this platform
446 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
447 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
450 #endif /* _ASM_MPC85xx_CONFIG_H_ */