2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
27 #define CONFIG_SYS_FSL_SEC_BE
28 #define CONFIG_SYS_FSL_SFP_BE
29 #define CONFIG_SYS_FSL_SEC_MON_BE
31 /* Number of TLB CAM entries we have on FSL Book-E chips */
32 #if defined(CONFIG_E500MC)
33 #define CONFIG_SYS_NUM_TLBCAMS 64
34 #elif defined(CONFIG_E500)
35 #define CONFIG_SYS_NUM_TLBCAMS 16
38 #if defined(CONFIG_ARCH_MPC8536)
39 #define CONFIG_SYS_FSL_NUM_LAWS 12
40 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
41 #define CONFIG_SYS_FSL_SEC_COMPAT 2
42 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #define CONFIG_SYS_FSL_ERRATUM_A004508
44 #define CONFIG_SYS_FSL_ERRATUM_A005125
46 #elif defined(CONFIG_ARCH_MPC8540)
47 #define CONFIG_SYS_FSL_NUM_LAWS 8
48 #define CONFIG_SYS_FSL_DDRC_GEN1
49 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
51 #elif defined(CONFIG_ARCH_MPC8541)
52 #define CONFIG_SYS_FSL_NUM_LAWS 8
53 #define CONFIG_SYS_FSL_DDRC_GEN1
54 #define CONFIG_SYS_FSL_SEC_COMPAT 2
55 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
57 #elif defined(CONFIG_ARCH_MPC8544)
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
63 #define CONFIG_SYS_FSL_ERRATUM_A005125
65 #elif defined(CONFIG_ARCH_MPC8548)
66 #define CONFIG_SYS_FSL_NUM_LAWS 10
67 #define CONFIG_SYS_FSL_DDRC_GEN2
68 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
69 #define CONFIG_SYS_FSL_SEC_COMPAT 2
70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
71 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
72 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
73 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
74 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
75 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
76 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
77 #define CONFIG_SYS_FSL_RMU
78 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
79 #define CONFIG_SYS_FSL_ERRATUM_A005125
80 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
81 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
83 #elif defined(CONFIG_ARCH_MPC8555)
84 #define CONFIG_SYS_FSL_NUM_LAWS 8
85 #define CONFIG_SYS_FSL_DDRC_GEN1
86 #define CONFIG_SYS_FSL_SEC_COMPAT 2
87 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
89 #elif defined(CONFIG_ARCH_MPC8560)
90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
94 #elif defined(CONFIG_ARCH_MPC8568)
95 #define CONFIG_SYS_FSL_NUM_LAWS 10
96 #define CONFIG_SYS_FSL_DDRC_GEN2
97 #define CONFIG_SYS_FSL_SEC_COMPAT 2
98 #define QE_MURAM_SIZE 0x10000UL
100 #define QE_NUM_OF_SNUM 28
101 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
102 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
103 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
104 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
105 #define CONFIG_SYS_FSL_RMU
106 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
108 #elif defined(CONFIG_ARCH_MPC8569)
109 #define CONFIG_SYS_FSL_NUM_LAWS 10
110 #define CONFIG_SYS_FSL_SEC_COMPAT 2
111 #define QE_MURAM_SIZE 0x20000UL
112 #define MAX_QE_RISC 4
113 #define QE_NUM_OF_SNUM 46
114 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
115 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
116 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
117 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
118 #define CONFIG_SYS_FSL_RMU
119 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
120 #define CONFIG_SYS_FSL_ERRATUM_A004508
121 #define CONFIG_SYS_FSL_ERRATUM_A005125
123 #elif defined(CONFIG_ARCH_MPC8572)
124 #define CONFIG_SYS_FSL_NUM_LAWS 12
125 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
126 #define CONFIG_SYS_FSL_SEC_COMPAT 2
127 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
128 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
129 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
130 #define CONFIG_SYS_FSL_ERRATUM_A004508
131 #define CONFIG_SYS_FSL_ERRATUM_A005125
133 #elif defined(CONFIG_ARCH_P1010)
134 #define CONFIG_FSL_SDHC_V2_3
135 #define CONFIG_SYS_FSL_NUM_LAWS 12
136 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
137 #define CONFIG_TSECV2
138 #define CONFIG_SYS_FSL_SEC_COMPAT 4
139 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
140 #define CONFIG_NUM_DDR_CONTROLLERS 1
141 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
142 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
143 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
144 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
145 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
146 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
147 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
148 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
149 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
150 #define CONFIG_SYS_FSL_ERRATUM_A005125
151 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
152 #define CONFIG_SYS_FSL_ERRATUM_A004508
153 #define CONFIG_SYS_FSL_ERRATUM_A007075
154 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
155 #define CONFIG_SYS_FSL_ERRATUM_A006261
156 #define CONFIG_SYS_FSL_ERRATUM_A004477
157 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
158 #define CONFIG_ESDHC_HC_BLK_ADDR
160 /* P1011 is single core version of P1020 */
161 #elif defined(CONFIG_ARCH_P1011)
162 #define CONFIG_SYS_FSL_NUM_LAWS 12
163 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
164 #define CONFIG_TSECV2
165 #define CONFIG_FSL_PCIE_DISABLE_ASPM
166 #define CONFIG_SYS_FSL_SEC_COMPAT 2
167 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
168 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
169 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
170 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
171 #define CONFIG_SYS_FSL_ERRATUM_A004508
172 #define CONFIG_SYS_FSL_ERRATUM_A005125
174 #elif defined(CONFIG_ARCH_P1020)
175 #define CONFIG_SYS_FSL_NUM_LAWS 12
176 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
177 #define CONFIG_TSECV2
178 #define CONFIG_FSL_PCIE_DISABLE_ASPM
179 #define CONFIG_SYS_FSL_SEC_COMPAT 2
180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 #define CONFIG_SYS_FSL_ERRATUM_A004508
184 #define CONFIG_SYS_FSL_ERRATUM_A005125
185 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
186 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
189 #elif defined(CONFIG_ARCH_P1021)
190 #define CONFIG_SYS_FSL_NUM_LAWS 12
191 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
192 #define CONFIG_TSECV2
193 #define CONFIG_FSL_PCIE_DISABLE_ASPM
194 #define CONFIG_SYS_FSL_SEC_COMPAT 2
195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
196 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
198 #define QE_MURAM_SIZE 0x6000UL
199 #define MAX_QE_RISC 1
200 #define QE_NUM_OF_SNUM 28
201 #define CONFIG_SYS_FSL_ERRATUM_A004508
202 #define CONFIG_SYS_FSL_ERRATUM_A005125
203 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
205 #elif defined(CONFIG_ARCH_P1022)
206 #define CONFIG_SYS_FSL_NUM_LAWS 12
207 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
208 #define CONFIG_TSECV2
209 #define CONFIG_SYS_FSL_SEC_COMPAT 2
210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
212 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
214 #define CONFIG_FSL_SATA_ERRATUM_A001
215 #define CONFIG_SYS_FSL_ERRATUM_A004508
216 #define CONFIG_SYS_FSL_ERRATUM_A005125
217 #define CONFIG_SYS_FSL_ERRATUM_A004477
219 #elif defined(CONFIG_ARCH_P1023)
220 #define CONFIG_SYS_FSL_NUM_LAWS 12
221 #define CONFIG_SYS_FSL_SEC_COMPAT 4
222 #define CONFIG_SYS_NUM_FMAN 1
223 #define CONFIG_SYS_NUM_FM1_DTSEC 2
224 #define CONFIG_NUM_DDR_CONTROLLERS 1
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
227 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
228 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
229 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
230 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
231 #define CONFIG_SYS_FSL_ERRATUM_A004508
232 #define CONFIG_SYS_FSL_ERRATUM_A005125
233 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
234 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
236 /* P1024 is lower end variant of P1020 */
237 #elif defined(CONFIG_ARCH_P1024)
238 #define CONFIG_SYS_FSL_NUM_LAWS 12
239 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
240 #define CONFIG_TSECV2
241 #define CONFIG_FSL_PCIE_DISABLE_ASPM
242 #define CONFIG_SYS_FSL_SEC_COMPAT 2
243 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247 #define CONFIG_SYS_FSL_ERRATUM_A004508
248 #define CONFIG_SYS_FSL_ERRATUM_A005125
250 /* P1025 is lower end variant of P1021 */
251 #elif defined(CONFIG_ARCH_P1025)
252 #define CONFIG_SYS_FSL_NUM_LAWS 12
253 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
255 #define CONFIG_TSECV2
256 #define CONFIG_FSL_PCIE_DISABLE_ASPM
257 #define CONFIG_SYS_FSL_SEC_COMPAT 2
258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
261 #define QE_MURAM_SIZE 0x6000UL
262 #define MAX_QE_RISC 1
263 #define QE_NUM_OF_SNUM 28
264 #define CONFIG_SYS_FSL_ERRATUM_A004508
265 #define CONFIG_SYS_FSL_ERRATUM_A005125
267 #elif defined(CONFIG_ARCH_P2020)
268 #define CONFIG_SYS_FSL_NUM_LAWS 12
269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
270 #define CONFIG_SYS_FSL_SEC_COMPAT 2
271 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
272 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
273 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
274 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
275 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
276 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
277 #define CONFIG_SYS_FSL_RMU
278 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
279 #define CONFIG_SYS_FSL_ERRATUM_A004508
280 #define CONFIG_SYS_FSL_ERRATUM_A005125
281 #define CONFIG_SYS_FSL_ERRATUM_A004477
282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
284 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
285 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
286 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
287 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
288 #define CONFIG_SYS_FSL_NUM_LAWS 32
289 #define CONFIG_SYS_FSL_SEC_COMPAT 4
290 #define CONFIG_SYS_NUM_FMAN 1
291 #define CONFIG_SYS_NUM_FM1_DTSEC 5
292 #define CONFIG_SYS_NUM_FM1_10GEC 1
293 #define CONFIG_NUM_DDR_CONTROLLERS 1
294 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
295 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
296 #define CONFIG_SYS_FSL_TBCLK_DIV 32
297 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
298 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
299 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
300 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
301 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
302 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
303 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
304 #define CONFIG_SYS_FSL_ERRATUM_USB14
305 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
306 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
307 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
308 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
309 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
310 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
311 #define CONFIG_SYS_FSL_ERRATUM_A004510
312 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
313 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
314 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
315 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
316 #define CONFIG_SYS_FSL_ERRATUM_A004849
317 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
318 #define CONFIG_SYS_FSL_ERRATUM_A006261
319 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
321 #elif defined(CONFIG_ARCH_P3041)
322 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
323 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
324 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
325 #define CONFIG_SYS_FSL_NUM_LAWS 32
326 #define CONFIG_SYS_FSL_SEC_COMPAT 4
327 #define CONFIG_SYS_NUM_FMAN 1
328 #define CONFIG_SYS_NUM_FM1_DTSEC 5
329 #define CONFIG_SYS_NUM_FM1_10GEC 1
330 #define CONFIG_NUM_DDR_CONTROLLERS 1
331 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
332 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
333 #define CONFIG_SYS_FSL_TBCLK_DIV 32
334 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
336 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
337 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
338 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
339 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
340 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
341 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
342 #define CONFIG_SYS_FSL_ERRATUM_USB14
343 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
344 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
345 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
346 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
347 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
348 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
349 #define CONFIG_SYS_FSL_ERRATUM_A004510
350 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
351 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
352 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
353 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
354 #define CONFIG_SYS_FSL_ERRATUM_A004849
355 #define CONFIG_SYS_FSL_ERRATUM_A005812
356 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
357 #define CONFIG_SYS_FSL_ERRATUM_A006261
358 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
360 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
361 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
362 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
363 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
364 #define CONFIG_SYS_FSL_NUM_LAWS 32
365 #define CONFIG_SYS_FSL_SEC_COMPAT 4
366 #define CONFIG_SYS_NUM_FMAN 2
367 #define CONFIG_SYS_NUM_FM1_DTSEC 4
368 #define CONFIG_SYS_NUM_FM2_DTSEC 4
369 #define CONFIG_SYS_NUM_FM1_10GEC 1
370 #define CONFIG_SYS_NUM_FM2_10GEC 1
371 #define CONFIG_NUM_DDR_CONTROLLERS 2
372 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
373 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
374 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
375 #define CONFIG_SYS_FSL_TBCLK_DIV 16
376 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
377 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
378 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
379 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
380 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
381 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
382 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
383 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
384 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
385 #define CONFIG_SYS_P4080_ERRATUM_CPU22
386 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
387 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
388 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
389 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
390 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
391 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
392 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
393 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
394 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
395 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
396 #define CONFIG_SYS_FSL_RMU
397 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
398 #define CONFIG_SYS_FSL_ERRATUM_A004510
399 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
400 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
401 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
402 #define CONFIG_SYS_FSL_ERRATUM_A004849
403 #define CONFIG_SYS_FSL_ERRATUM_A004580
404 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
405 #define CONFIG_SYS_FSL_ERRATUM_A005812
406 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
407 #define CONFIG_SYS_FSL_ERRATUM_A007075
408 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
410 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
411 #define CONFIG_SYS_PPC64 /* 64-bit core */
412 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
413 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
414 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
415 #define CONFIG_SYS_FSL_NUM_LAWS 32
416 #define CONFIG_SYS_FSL_SEC_COMPAT 4
417 #define CONFIG_SYS_NUM_FMAN 1
418 #define CONFIG_SYS_NUM_FM1_DTSEC 5
419 #define CONFIG_SYS_NUM_FM1_10GEC 1
420 #define CONFIG_NUM_DDR_CONTROLLERS 2
421 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
422 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
423 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
424 #define CONFIG_SYS_FSL_TBCLK_DIV 32
425 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
426 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
427 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
428 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
429 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
430 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
431 #define CONFIG_SYS_FSL_ERRATUM_USB14
432 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
433 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
434 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
435 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
436 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
437 #define CONFIG_SYS_FSL_ERRATUM_A004510
438 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
439 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
440 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
441 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
442 #define CONFIG_SYS_FSL_ERRATUM_A006261
443 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
445 #elif defined(CONFIG_ARCH_P5040)
446 #define CONFIG_SYS_PPC64
447 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
448 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
449 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
450 #define CONFIG_SYS_FSL_NUM_LAWS 32
451 #define CONFIG_SYS_FSL_SEC_COMPAT 4
452 #define CONFIG_SYS_NUM_FMAN 2
453 #define CONFIG_SYS_NUM_FM1_DTSEC 5
454 #define CONFIG_SYS_NUM_FM1_10GEC 1
455 #define CONFIG_SYS_NUM_FM2_DTSEC 5
456 #define CONFIG_SYS_NUM_FM2_10GEC 1
457 #define CONFIG_NUM_DDR_CONTROLLERS 2
458 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
459 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
460 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
461 #define CONFIG_SYS_FSL_TBCLK_DIV 16
462 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
463 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
464 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
465 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
466 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
467 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
468 #define CONFIG_SYS_FSL_ERRATUM_USB14
469 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
470 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
471 #define CONFIG_SYS_FSL_ERRATUM_A004699
472 #define CONFIG_SYS_FSL_ERRATUM_A004510
473 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
474 #define CONFIG_SYS_FSL_ERRATUM_A006261
475 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
476 #define CONFIG_SYS_FSL_ERRATUM_A005812
478 #elif defined(CONFIG_ARCH_BSC9131)
479 #define CONFIG_FSL_SDHC_V2_3
480 #define CONFIG_SYS_FSL_NUM_LAWS 12
481 #define CONFIG_TSECV2
482 #define CONFIG_SYS_FSL_SEC_COMPAT 4
483 #define CONFIG_NUM_DDR_CONTROLLERS 1
484 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
485 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
486 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
487 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
488 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
489 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
490 #define CONFIG_NAND_FSL_IFC
491 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
492 #define CONFIG_SYS_FSL_ERRATUM_A005125
493 #define CONFIG_SYS_FSL_ERRATUM_A004477
494 #define CONFIG_ESDHC_HC_BLK_ADDR
496 #elif defined(CONFIG_ARCH_BSC9132)
497 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
498 #define CONFIG_FSL_SDHC_V2_3
499 #define CONFIG_SYS_FSL_NUM_LAWS 12
500 #define CONFIG_TSECV2
501 #define CONFIG_SYS_FSL_SEC_COMPAT 4
502 #define CONFIG_NUM_DDR_CONTROLLERS 2
503 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
504 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
505 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
506 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
507 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
508 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
509 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
510 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
511 #define CONFIG_NAND_FSL_IFC
512 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
513 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
514 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
515 #define CONFIG_SYS_FSL_ERRATUM_A005125
516 #define CONFIG_SYS_FSL_ERRATUM_A005434
517 #define CONFIG_SYS_FSL_ERRATUM_A004477
518 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
519 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
520 #define CONFIG_ESDHC_HC_BLK_ADDR
522 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
524 #define CONFIG_SYS_PPC64 /* 64-bit core */
525 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
526 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
527 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
528 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
529 #ifdef CONFIG_ARCH_T4240
530 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
531 #define CONFIG_SYS_NUM_FM1_DTSEC 8
532 #define CONFIG_SYS_NUM_FM1_10GEC 2
533 #define CONFIG_SYS_NUM_FM2_DTSEC 8
534 #define CONFIG_SYS_NUM_FM2_10GEC 2
535 #define CONFIG_NUM_DDR_CONTROLLERS 3
536 #define CONFIG_SYS_FSL_ERRATUM_A006261
538 #define CONFIG_SYS_NUM_FM1_DTSEC 6
539 #define CONFIG_SYS_NUM_FM1_10GEC 1
540 #define CONFIG_SYS_NUM_FM2_DTSEC 8
541 #define CONFIG_SYS_NUM_FM2_10GEC 1
542 #define CONFIG_NUM_DDR_CONTROLLERS 2
543 #if defined(CONFIG_ARCH_T4160)
544 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
547 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
548 #define CONFIG_SYS_FSL_NUM_LAWS 32
549 #define CONFIG_SYS_FSL_SRDS_1
550 #define CONFIG_SYS_FSL_SRDS_2
551 #define CONFIG_SYS_FSL_SRDS_3
552 #define CONFIG_SYS_FSL_SRDS_4
553 #define CONFIG_SYS_FSL_SEC_COMPAT 4
554 #define CONFIG_SYS_NUM_FMAN 2
555 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
556 #define CONFIG_SYS_PME_CLK 0
557 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
558 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
559 #define CONFIG_SYS_FMAN_V3
560 #define CONFIG_SYS_FM1_CLK 3
561 #define CONFIG_SYS_FM2_CLK 3
562 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
563 #define CONFIG_SYS_FSL_TBCLK_DIV 16
564 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
565 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
566 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
567 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
568 #define CONFIG_SYS_FSL_SRIO_LIODN
569 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
570 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
571 #define CONFIG_SYS_FSL_ERRATUM_A004468
572 #define CONFIG_SYS_FSL_ERRATUM_A_004934
573 #define CONFIG_SYS_FSL_ERRATUM_A005871
574 #define CONFIG_SYS_FSL_ERRATUM_A006379
575 #define CONFIG_SYS_FSL_ERRATUM_A007186
576 #define CONFIG_SYS_FSL_ERRATUM_A006593
577 #define CONFIG_SYS_FSL_ERRATUM_A007798
578 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
579 #define CONFIG_SYS_FSL_SFP_VER_3_0
580 #define CONFIG_SYS_FSL_PCI_VER_3_X
582 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
584 #define CONFIG_SYS_PPC64 /* 64-bit core */
585 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
586 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
587 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
588 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
589 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
590 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
591 #define CONFIG_SYS_FSL_NUM_LAWS 32
592 #define CONFIG_SYS_FSL_SRDS_1
593 #define CONFIG_SYS_FSL_SRDS_2
594 #define CONFIG_SYS_MAPLE
595 #define CONFIG_SYS_CPRI
596 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
597 #define CONFIG_SYS_FSL_SEC_COMPAT 4
598 #define CONFIG_SYS_NUM_FMAN 1
599 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
600 #define CONFIG_SYS_FM1_CLK 0
601 #define CONFIG_SYS_CPRI_CLK 3
602 #define CONFIG_SYS_ULB_CLK 4
603 #define CONFIG_SYS_ETVPE_CLK 1
604 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
605 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
606 #define CONFIG_SYS_FMAN_V3
607 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
608 #define CONFIG_SYS_FSL_TBCLK_DIV 16
609 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
610 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
611 #define CONFIG_SYS_FSL_ERRATUM_A_004934
612 #define CONFIG_SYS_FSL_ERRATUM_A005871
613 #define CONFIG_SYS_FSL_ERRATUM_A006379
614 #define CONFIG_SYS_FSL_ERRATUM_A007186
615 #define CONFIG_SYS_FSL_ERRATUM_A006593
616 #define CONFIG_SYS_FSL_ERRATUM_A007075
617 #define CONFIG_SYS_FSL_ERRATUM_A006475
618 #define CONFIG_SYS_FSL_ERRATUM_A006384
619 #define CONFIG_SYS_FSL_ERRATUM_A007212
620 #define CONFIG_SYS_FSL_ERRATUM_A004477
621 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
622 #define CONFIG_SYS_FSL_SFP_VER_3_0
624 #ifdef CONFIG_ARCH_B4860
625 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
626 #define CONFIG_MAX_DSP_CPUS 12
627 #define CONFIG_NUM_DSP_CPUS 6
628 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
629 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
630 #define CONFIG_SYS_NUM_FM1_DTSEC 6
631 #define CONFIG_SYS_NUM_FM1_10GEC 2
632 #define CONFIG_NUM_DDR_CONTROLLERS 2
633 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
634 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
635 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
636 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
637 #define CONFIG_SYS_FSL_SRIO_LIODN
639 #define CONFIG_MAX_DSP_CPUS 2
640 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
641 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
642 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
643 #define CONFIG_SYS_NUM_FM1_DTSEC 4
644 #define CONFIG_SYS_NUM_FM1_10GEC 0
645 #define CONFIG_NUM_DDR_CONTROLLERS 1
648 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
649 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
651 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
652 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
653 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
654 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
655 #ifdef CONFIG_SYS_FSL_DDR4
656 #define CONFIG_SYS_FSL_DDRC_GEN4
658 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
659 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
660 #define CONFIG_SYS_FSL_NUM_LAWS 16
661 #define CONFIG_SYS_FSL_SRDS_1
662 #define CONFIG_SYS_FSL_SEC_COMPAT 5
663 #define CONFIG_SYS_NUM_FMAN 1
664 #define CONFIG_SYS_NUM_FM1_DTSEC 5
665 #define CONFIG_NUM_DDR_CONTROLLERS 1
666 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
667 #define CONFIG_PME_PLAT_CLK_DIV 2
668 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
669 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
670 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
671 #define CONFIG_SYS_FSL_ERRATUM_A008044
672 #define CONFIG_SYS_FMAN_V3
673 #define CONFIG_FM_PLAT_CLK_DIV 1
674 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
675 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
676 per rcw field value */
677 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
678 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
679 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
680 #define CONFIG_SYS_FSL_TBCLK_DIV 16
681 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
682 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
683 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
684 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
685 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
686 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
687 #define QE_MURAM_SIZE 0x6000UL
688 #define MAX_QE_RISC 1
689 #define QE_NUM_OF_SNUM 28
690 #define CONFIG_SYS_FSL_SFP_VER_3_0
691 #define CONFIG_SYS_FSL_ERRATUM_A008378
692 #define CONFIG_SYS_FSL_ERRATUM_A009663
694 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
695 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
697 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
698 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
699 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
700 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
701 #define CONFIG_SYS_FMAN_V3
702 #ifdef CONFIG_SYS_FSL_DDR4
703 #define CONFIG_SYS_FSL_DDRC_GEN4
705 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
706 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
707 #define CONFIG_SYS_FSL_NUM_LAWS 16
708 #define CONFIG_SYS_FSL_SRDS_1
709 #define CONFIG_SYS_FSL_SEC_COMPAT 5
710 #define CONFIG_SYS_NUM_FMAN 1
711 #define CONFIG_SYS_NUM_FM1_DTSEC 4
712 #define CONFIG_SYS_NUM_FM1_10GEC 1
713 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
714 #define CONFIG_NUM_DDR_CONTROLLERS 1
715 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
716 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
717 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
718 #define CONFIG_SYS_FM1_CLK 0
719 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
720 per rcw field value */
721 #define CONFIG_QBMAN_CLK_DIV 1
722 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
723 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
724 #define CONFIG_SYS_FSL_TBCLK_DIV 16
725 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
726 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
727 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
728 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
729 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
730 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
731 #define QE_MURAM_SIZE 0x6000UL
732 #define MAX_QE_RISC 1
733 #define QE_NUM_OF_SNUM 28
734 #define CONFIG_SYS_FSL_SFP_VER_3_0
735 #define CONFIG_SYS_FSL_ERRATUM_A008378
736 #define CONFIG_SYS_FSL_ERRATUM_A009663
738 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
740 #define CONFIG_SYS_PPC64 /* 64-bit core */
741 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
742 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
743 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
744 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
745 #define CONFIG_SYS_FSL_QMAN_V3
746 #define CONFIG_SYS_FSL_NUM_LAWS 32
747 #define CONFIG_SYS_FSL_SEC_COMPAT 4
748 #define CONFIG_SYS_NUM_FMAN 1
749 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
750 #define CONFIG_SYS_FSL_SRDS_1
751 #define CONFIG_SYS_FSL_PCI_VER_3_X
752 #if defined(CONFIG_ARCH_T2080)
753 #define CONFIG_SYS_NUM_FM1_DTSEC 8
754 #define CONFIG_SYS_NUM_FM1_10GEC 4
755 #define CONFIG_SYS_FSL_SRDS_2
756 #define CONFIG_SYS_FSL_SRIO_LIODN
757 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
758 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
759 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
760 #elif defined(CONFIG_ARCH_T2081)
761 #define CONFIG_SYS_NUM_FM1_DTSEC 6
762 #define CONFIG_SYS_NUM_FM1_10GEC 2
764 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
765 #define CONFIG_NUM_DDR_CONTROLLERS 1
766 #define CONFIG_PME_PLAT_CLK_DIV 1
767 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
768 #define CONFIG_SYS_FM1_CLK 0
769 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
770 per rcw field value */
771 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
772 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
773 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
774 #define CONFIG_SYS_FMAN_V3
775 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
776 #define CONFIG_SYS_FSL_TBCLK_DIV 16
777 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
778 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
779 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
780 #define CONFIG_SYS_FSL_ERRATUM_A007212
781 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
782 #define CONFIG_SYS_FSL_SFP_VER_3_0
783 #define CONFIG_SYS_FSL_ISBC_VER 2
784 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
785 #define CONFIG_SYS_FSL_ERRATUM_A006593
786 #define CONFIG_SYS_FSL_ERRATUM_A007186
787 #define CONFIG_SYS_FSL_ERRATUM_A006379
788 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
789 #define CONFIG_SYS_FSL_SFP_VER_3_0
792 #elif defined(CONFIG_ARCH_C29X)
793 #define CONFIG_FSL_SDHC_V2_3
794 #define CONFIG_SYS_FSL_NUM_LAWS 12
795 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
796 #define CONFIG_TSECV2_1
797 #define CONFIG_SYS_FSL_SEC_COMPAT 6
798 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
799 #define CONFIG_NUM_DDR_CONTROLLERS 1
800 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
801 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
802 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
803 #define CONFIG_SYS_FSL_ERRATUM_A005125
804 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
805 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
807 #elif defined(CONFIG_ARCH_QEMU_E500)
808 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
811 #error Processor type not defined for this platform
814 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
815 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
819 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
821 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
824 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
825 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
826 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
827 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
828 #define CONFIG_SYS_FSL_DDRC_GEN3
831 #if !defined(CONFIG_ARCH_C29X)
832 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
835 #endif /* _ASM_MPC85xx_CONFIG_H_ */