2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #define FSL_DDR_VER_4_7 47
24 /* Number of TLB CAM entries we have on FSL Book-E chips */
25 #if defined(CONFIG_E500MC)
26 #define CONFIG_SYS_NUM_TLBCAMS 64
27 #elif defined(CONFIG_E500)
28 #define CONFIG_SYS_NUM_TLBCAMS 16
31 #if defined(CONFIG_MPC8536)
32 #define CONFIG_MAX_CPUS 1
33 #define CONFIG_SYS_FSL_NUM_LAWS 12
34 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
35 #define CONFIG_SYS_FSL_SEC_COMPAT 2
36 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
38 #elif defined(CONFIG_MPC8540)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 8
41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #elif defined(CONFIG_MPC8541)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
49 #elif defined(CONFIG_MPC8544)
50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 10
52 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
56 #elif defined(CONFIG_MPC8548)
57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
60 #define CONFIG_SYS_FSL_SEC_COMPAT 2
61 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
62 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
63 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
64 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
68 #define CONFIG_SYS_FSL_RMU
69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
71 #elif defined(CONFIG_MPC8555)
72 #define CONFIG_MAX_CPUS 1
73 #define CONFIG_SYS_FSL_NUM_LAWS 8
74 #define CONFIG_SYS_FSL_SEC_COMPAT 2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
77 #elif defined(CONFIG_MPC8560)
78 #define CONFIG_MAX_CPUS 1
79 #define CONFIG_SYS_FSL_NUM_LAWS 8
80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
82 #elif defined(CONFIG_MPC8568)
83 #define CONFIG_MAX_CPUS 1
84 #define CONFIG_SYS_FSL_NUM_LAWS 10
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define QE_MURAM_SIZE 0x10000UL
88 #define QE_NUM_OF_SNUM 28
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
90 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
91 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
92 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
93 #define CONFIG_SYS_FSL_RMU
94 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
96 #elif defined(CONFIG_MPC8569)
97 #define CONFIG_MAX_CPUS 1
98 #define CONFIG_SYS_FSL_NUM_LAWS 10
99 #define CONFIG_SYS_FSL_SEC_COMPAT 2
100 #define QE_MURAM_SIZE 0x20000UL
101 #define MAX_QE_RISC 4
102 #define QE_NUM_OF_SNUM 46
103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
104 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
105 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107 #define CONFIG_SYS_FSL_RMU
108 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
110 #elif defined(CONFIG_MPC8572)
111 #define CONFIG_MAX_CPUS 2
112 #define CONFIG_SYS_FSL_NUM_LAWS 12
113 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
114 #define CONFIG_SYS_FSL_SEC_COMPAT 2
115 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
116 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
117 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
119 #elif defined(CONFIG_P1010)
120 #define CONFIG_MAX_CPUS 1
121 #define CONFIG_FSL_SDHC_V2_3
122 #define CONFIG_SYS_FSL_NUM_LAWS 12
123 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
124 #define CONFIG_TSECV2
125 #define CONFIG_SYS_FSL_SEC_COMPAT 4
126 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
127 #define CONFIG_NUM_DDR_CONTROLLERS 1
128 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
131 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
132 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
133 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
134 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
135 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
137 /* P1011 is single core version of P1020 */
138 #elif defined(CONFIG_P1011)
139 #define CONFIG_MAX_CPUS 1
140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
142 #define CONFIG_TSECV2
143 #define CONFIG_FSL_PCIE_DISABLE_ASPM
144 #define CONFIG_SYS_FSL_SEC_COMPAT 2
145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
146 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
147 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
149 /* P1012 is single core version of P1021 */
150 #elif defined(CONFIG_P1012)
151 #define CONFIG_MAX_CPUS 1
152 #define CONFIG_SYS_FSL_NUM_LAWS 12
153 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
154 #define CONFIG_TSECV2
155 #define CONFIG_FSL_PCIE_DISABLE_ASPM
156 #define CONFIG_SYS_FSL_SEC_COMPAT 2
157 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
158 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
159 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
160 #define QE_MURAM_SIZE 0x6000UL
161 #define MAX_QE_RISC 1
162 #define QE_NUM_OF_SNUM 28
164 /* P1013 is single core version of P1022 */
165 #elif defined(CONFIG_P1013)
166 #define CONFIG_MAX_CPUS 1
167 #define CONFIG_SYS_FSL_NUM_LAWS 12
168 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
169 #define CONFIG_TSECV2
170 #define CONFIG_SYS_FSL_SEC_COMPAT 2
171 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
174 #define CONFIG_FSL_SATA_ERRATUM_A001
176 #elif defined(CONFIG_P1014)
177 #define CONFIG_MAX_CPUS 1
178 #define CONFIG_FSL_SDHC_V2_3
179 #define CONFIG_SYS_FSL_NUM_LAWS 12
180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
181 #define CONFIG_TSECV2
182 #define CONFIG_SYS_FSL_SEC_COMPAT 4
183 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
184 #define CONFIG_NUM_DDR_CONTROLLERS 1
185 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
186 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
187 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
188 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
189 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
191 /* P1017 is single core version of P1023 */
192 #elif defined(CONFIG_P1017)
193 #define CONFIG_MAX_CPUS 1
194 #define CONFIG_SYS_FSL_NUM_LAWS 12
195 #define CONFIG_SYS_FSL_SEC_COMPAT 4
196 #define CONFIG_SYS_NUM_FMAN 1
197 #define CONFIG_SYS_NUM_FM1_DTSEC 2
198 #define CONFIG_NUM_DDR_CONTROLLERS 1
199 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
200 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
201 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
202 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
203 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
205 #elif defined(CONFIG_P1020)
206 #define CONFIG_MAX_CPUS 2
207 #define CONFIG_SYS_FSL_NUM_LAWS 12
208 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
209 #define CONFIG_TSECV2
210 #define CONFIG_FSL_PCIE_DISABLE_ASPM
211 #define CONFIG_SYS_FSL_SEC_COMPAT 2
212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
213 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
214 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
216 #elif defined(CONFIG_P1021)
217 #define CONFIG_MAX_CPUS 2
218 #define CONFIG_SYS_FSL_NUM_LAWS 12
219 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
220 #define CONFIG_TSECV2
221 #define CONFIG_FSL_PCIE_DISABLE_ASPM
222 #define CONFIG_SYS_FSL_SEC_COMPAT 2
223 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
224 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
226 #define QE_MURAM_SIZE 0x6000UL
227 #define MAX_QE_RISC 1
228 #define QE_NUM_OF_SNUM 28
230 #elif defined(CONFIG_P1022)
231 #define CONFIG_MAX_CPUS 2
232 #define CONFIG_SYS_FSL_NUM_LAWS 12
233 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
234 #define CONFIG_TSECV2
235 #define CONFIG_SYS_FSL_SEC_COMPAT 2
236 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
237 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
238 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
239 #define CONFIG_FSL_SATA_ERRATUM_A001
241 #elif defined(CONFIG_P1023)
242 #define CONFIG_MAX_CPUS 2
243 #define CONFIG_SYS_FSL_NUM_LAWS 12
244 #define CONFIG_SYS_FSL_SEC_COMPAT 4
245 #define CONFIG_SYS_NUM_FMAN 1
246 #define CONFIG_SYS_NUM_FM1_DTSEC 2
247 #define CONFIG_NUM_DDR_CONTROLLERS 1
248 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
249 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
250 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
251 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
252 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
254 /* P1024 is lower end variant of P1020 */
255 #elif defined(CONFIG_P1024)
256 #define CONFIG_MAX_CPUS 2
257 #define CONFIG_SYS_FSL_NUM_LAWS 12
258 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
259 #define CONFIG_TSECV2
260 #define CONFIG_FSL_PCIE_DISABLE_ASPM
261 #define CONFIG_SYS_FSL_SEC_COMPAT 2
262 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
263 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
264 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
266 /* P1025 is lower end variant of P1021 */
267 #elif defined(CONFIG_P1025)
268 #define CONFIG_MAX_CPUS 2
269 #define CONFIG_SYS_FSL_NUM_LAWS 12
270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
271 #define CONFIG_TSECV2
272 #define CONFIG_FSL_PCIE_DISABLE_ASPM
273 #define CONFIG_SYS_FSL_SEC_COMPAT 2
274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277 #define QE_MURAM_SIZE 0x6000UL
278 #define MAX_QE_RISC 1
279 #define QE_NUM_OF_SNUM 28
281 /* P2010 is single core version of P2020 */
282 #elif defined(CONFIG_P2010)
283 #define CONFIG_MAX_CPUS 1
284 #define CONFIG_SYS_FSL_NUM_LAWS 12
285 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
286 #define CONFIG_SYS_FSL_SEC_COMPAT 2
287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
289 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
291 #elif defined(CONFIG_P2020)
292 #define CONFIG_MAX_CPUS 2
293 #define CONFIG_SYS_FSL_NUM_LAWS 12
294 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
295 #define CONFIG_SYS_FSL_SEC_COMPAT 2
296 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
298 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
299 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
300 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
301 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
302 #define CONFIG_SYS_FSL_RMU
303 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
305 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
306 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
307 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
308 #define CONFIG_MAX_CPUS 4
309 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
310 #define CONFIG_SYS_FSL_NUM_LAWS 32
311 #define CONFIG_SYS_FSL_SEC_COMPAT 4
312 #define CONFIG_SYS_NUM_FMAN 1
313 #define CONFIG_SYS_NUM_FM1_DTSEC 5
314 #define CONFIG_SYS_NUM_FM1_10GEC 1
315 #define CONFIG_NUM_DDR_CONTROLLERS 1
316 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
317 #define CONFIG_SYS_FSL_TBCLK_DIV 32
318 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
319 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
320 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
321 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
322 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
323 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
324 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
325 #define CONFIG_SYS_FSL_ERRATUM_USB14
326 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
327 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
328 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
329 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
330 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
331 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
332 #define CONFIG_SYS_FSL_ERRATUM_A004510
333 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
334 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
335 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
336 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
337 #define CONFIG_SYS_FSL_ERRATUM_A004849
339 #elif defined(CONFIG_PPC_P3041)
340 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
341 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
342 #define CONFIG_MAX_CPUS 4
343 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
344 #define CONFIG_SYS_FSL_NUM_LAWS 32
345 #define CONFIG_SYS_FSL_SEC_COMPAT 4
346 #define CONFIG_SYS_NUM_FMAN 1
347 #define CONFIG_SYS_NUM_FM1_DTSEC 5
348 #define CONFIG_SYS_NUM_FM1_10GEC 1
349 #define CONFIG_NUM_DDR_CONTROLLERS 1
350 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
351 #define CONFIG_SYS_FSL_TBCLK_DIV 32
352 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
353 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
354 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
355 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
356 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
357 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
358 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
359 #define CONFIG_SYS_FSL_ERRATUM_USB14
360 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
361 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
362 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
363 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
364 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
365 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
366 #define CONFIG_SYS_FSL_ERRATUM_A004510
367 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
368 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
369 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
370 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
371 #define CONFIG_SYS_FSL_ERRATUM_A004849
372 #define CONFIG_SYS_FSL_ERRATUM_A005812
374 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
375 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
376 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
377 #define CONFIG_MAX_CPUS 8
378 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
379 #define CONFIG_SYS_FSL_NUM_LAWS 32
380 #define CONFIG_SYS_FSL_SEC_COMPAT 4
381 #define CONFIG_SYS_NUM_FMAN 2
382 #define CONFIG_SYS_NUM_FM1_DTSEC 4
383 #define CONFIG_SYS_NUM_FM2_DTSEC 4
384 #define CONFIG_SYS_NUM_FM1_10GEC 1
385 #define CONFIG_SYS_NUM_FM2_10GEC 1
386 #define CONFIG_NUM_DDR_CONTROLLERS 2
387 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
388 #define CONFIG_SYS_FSL_TBCLK_DIV 16
389 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
390 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
391 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
392 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
393 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
394 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
395 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
396 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
397 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
398 #define CONFIG_SYS_P4080_ERRATUM_CPU22
399 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
400 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
401 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
402 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
403 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
404 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
406 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
407 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
408 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
409 #define CONFIG_SYS_FSL_RMU
410 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
411 #define CONFIG_SYS_FSL_ERRATUM_A004510
412 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
413 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
414 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
415 #define CONFIG_SYS_FSL_ERRATUM_A004849
416 #define CONFIG_SYS_FSL_ERRATUM_A004580
417 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
418 #define CONFIG_SYS_FSL_ERRATUM_A005812
420 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
421 #define CONFIG_SYS_PPC64 /* 64-bit core */
422 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
423 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
424 #define CONFIG_MAX_CPUS 2
425 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
426 #define CONFIG_SYS_FSL_NUM_LAWS 32
427 #define CONFIG_SYS_FSL_SEC_COMPAT 4
428 #define CONFIG_SYS_NUM_FMAN 1
429 #define CONFIG_SYS_NUM_FM1_DTSEC 5
430 #define CONFIG_SYS_NUM_FM1_10GEC 1
431 #define CONFIG_NUM_DDR_CONTROLLERS 2
432 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
433 #define CONFIG_SYS_FSL_TBCLK_DIV 32
434 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
435 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
436 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
437 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
438 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
439 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
440 #define CONFIG_SYS_FSL_ERRATUM_USB14
441 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
442 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
443 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
444 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
445 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
446 #define CONFIG_SYS_FSL_ERRATUM_A004510
447 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
448 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
449 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
451 #elif defined(CONFIG_PPC_P5040)
452 #define CONFIG_SYS_PPC64
453 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
454 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
455 #define CONFIG_MAX_CPUS 4
456 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
457 #define CONFIG_SYS_FSL_NUM_LAWS 32
458 #define CONFIG_SYS_FSL_SEC_COMPAT 4
459 #define CONFIG_SYS_NUM_FMAN 2
460 #define CONFIG_SYS_NUM_FM1_DTSEC 5
461 #define CONFIG_SYS_NUM_FM1_10GEC 1
462 #define CONFIG_SYS_NUM_FM2_DTSEC 5
463 #define CONFIG_SYS_NUM_FM2_10GEC 1
464 #define CONFIG_NUM_DDR_CONTROLLERS 2
465 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
466 #define CONFIG_SYS_FSL_TBCLK_DIV 16
467 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
468 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
469 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
470 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
471 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
472 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
473 #define CONFIG_SYS_FSL_ERRATUM_USB14
474 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
475 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
476 #define CONFIG_SYS_FSL_ERRATUM_A004699
477 #define CONFIG_SYS_FSL_ERRATUM_A004510
478 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
479 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
480 #define CONFIG_SYS_FSL_ERRATUM_A005812
482 #elif defined(CONFIG_BSC9131)
483 #define CONFIG_MAX_CPUS 1
484 #define CONFIG_FSL_SDHC_V2_3
485 #define CONFIG_SYS_FSL_NUM_LAWS 12
486 #define CONFIG_TSECV2
487 #define CONFIG_SYS_FSL_SEC_COMPAT 4
488 #define CONFIG_NUM_DDR_CONTROLLERS 1
489 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
490 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
491 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
492 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
493 #define CONFIG_NAND_FSL_IFC
494 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
496 #elif defined(CONFIG_BSC9132)
497 #define CONFIG_MAX_CPUS 2
498 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
499 #define CONFIG_FSL_SDHC_V2_3
500 #define CONFIG_SYS_FSL_NUM_LAWS 12
501 #define CONFIG_TSECV2
502 #define CONFIG_SYS_FSL_SEC_COMPAT 4
503 #define CONFIG_NUM_DDR_CONTROLLERS 2
504 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
505 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
506 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
507 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
508 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
509 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
510 #define CONFIG_NAND_FSL_IFC
511 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
512 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
513 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
515 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
517 #define CONFIG_SYS_PPC64 /* 64-bit core */
518 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
519 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
520 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
521 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
522 #ifdef CONFIG_PPC_T4240
523 #define CONFIG_MAX_CPUS 12
524 #define CONFIG_SYS_NUM_FM1_DTSEC 8
525 #define CONFIG_SYS_NUM_FM1_10GEC 2
526 #define CONFIG_SYS_NUM_FM2_DTSEC 8
527 #define CONFIG_SYS_NUM_FM2_10GEC 2
528 #define CONFIG_NUM_DDR_CONTROLLERS 3
530 #define CONFIG_MAX_CPUS 8
531 #define CONFIG_SYS_NUM_FM1_DTSEC 7
532 #define CONFIG_SYS_NUM_FM1_10GEC 1
533 #define CONFIG_SYS_NUM_FM2_DTSEC 7
534 #define CONFIG_SYS_NUM_FM2_10GEC 1
535 #define CONFIG_NUM_DDR_CONTROLLERS 2
537 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
538 #define CONFIG_SYS_FSL_NUM_LAWS 32
539 #define CONFIG_SYS_FSL_SRDS_1
540 #define CONFIG_SYS_FSL_SRDS_2
541 #define CONFIG_SYS_FSL_SRDS_3
542 #define CONFIG_SYS_FSL_SRDS_4
543 #define CONFIG_SYS_FSL_SEC_COMPAT 4
544 #define CONFIG_SYS_NUM_FMAN 2
545 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
546 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
547 #define CONFIG_SYS_FMAN_V3
548 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
549 #define CONFIG_SYS_FSL_TBCLK_DIV 16
550 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
551 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
552 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
553 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
554 #define CONFIG_SYS_FSL_SRIO_LIODN
555 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
556 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
557 #define CONFIG_SYS_FSL_ERRATUM_A004468
558 #define CONFIG_SYS_FSL_ERRATUM_A_004934
559 #define CONFIG_SYS_FSL_ERRATUM_A005871
560 #define CONFIG_SYS_FSL_ERRATUM_A006593
561 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
562 #define CONFIG_SYS_FSL_PCI_VER_3_X
564 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
566 #define CONFIG_SYS_PPC64 /* 64-bit core */
567 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
568 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
569 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
570 #define CONFIG_SYS_FSL_NUM_LAWS 32
571 #define CONFIG_SYS_FSL_SRDS_1
572 #define CONFIG_SYS_FSL_SRDS_2
573 #define CONFIG_SYS_FSL_SEC_COMPAT 4
574 #define CONFIG_SYS_NUM_FMAN 1
575 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
576 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
577 #define CONFIG_SYS_FMAN_V3
578 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
579 #define CONFIG_SYS_FSL_TBCLK_DIV 16
580 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
581 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
582 #define CONFIG_SYS_FSL_ERRATUM_A_004934
583 #define CONFIG_SYS_FSL_ERRATUM_A005871
584 #define CONFIG_SYS_FSL_ERRATUM_A006593
585 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
587 #ifdef CONFIG_PPC_B4860
588 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
589 #define CONFIG_MAX_CPUS 4
590 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
591 #define CONFIG_SYS_NUM_FM1_DTSEC 6
592 #define CONFIG_SYS_NUM_FM1_10GEC 2
593 #define CONFIG_NUM_DDR_CONTROLLERS 2
594 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
595 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
596 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
597 #define CONFIG_SYS_FSL_SRIO_LIODN
599 #define CONFIG_MAX_CPUS 2
600 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
601 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
602 #define CONFIG_SYS_NUM_FM1_DTSEC 4
603 #define CONFIG_SYS_NUM_FM1_10GEC 0
604 #define CONFIG_NUM_DDR_CONTROLLERS 1
607 #elif defined(CONFIG_PPC_T1040)
609 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
610 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
611 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
612 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
613 #define CONFIG_MAX_CPUS 4
614 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
615 #define CONFIG_SYS_FSL_NUM_LAWS 16
616 #define CONFIG_SYS_FSL_SEC_COMPAT 4
617 #define CONFIG_SYS_NUM_FMAN 1
618 #define CONFIG_SYS_NUM_FM1_DTSEC 5
619 #define CONFIG_NUM_DDR_CONTROLLERS 1
620 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
621 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
622 #define CONFIG_SYS_FMAN_V3
623 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
624 #define CONFIG_SYS_FSL_TBCLK_DIV 32
625 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
626 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
627 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
628 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
629 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
630 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
631 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
632 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
634 #elif defined(CONFIG_PPC_C29X)
635 #define CONFIG_MAX_CPUS 1
636 #define CONFIG_FSL_SDHC_V2_3
637 #define CONFIG_SYS_FSL_NUM_LAWS 12
638 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
639 #define CONFIG_TSECV2_1
640 #define CONFIG_SYS_FSL_SEC_COMPAT 6
641 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
642 #define CONFIG_NUM_DDR_CONTROLLERS 1
643 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
644 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
647 #error Processor type not defined for this platform
650 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
651 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
655 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
657 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
660 #endif /* _ASM_MPC85xx_CONFIG_H_ */