2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
27 #define CONFIG_SYS_FSL_SEC_BE
28 #define CONFIG_SYS_FSL_SFP_BE
30 /* Number of TLB CAM entries we have on FSL Book-E chips */
31 #if defined(CONFIG_E500MC)
32 #define CONFIG_SYS_NUM_TLBCAMS 64
33 #elif defined(CONFIG_E500)
34 #define CONFIG_SYS_NUM_TLBCAMS 16
37 #if defined(CONFIG_MPC8536)
38 #define CONFIG_MAX_CPUS 1
39 #define CONFIG_SYS_FSL_NUM_LAWS 12
40 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
41 #define CONFIG_SYS_FSL_SEC_COMPAT 2
42 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #define CONFIG_SYS_FSL_ERRATUM_A004508
44 #define CONFIG_SYS_FSL_ERRATUM_A005125
46 #elif defined(CONFIG_MPC8540)
47 #define CONFIG_MAX_CPUS 1
48 #define CONFIG_SYS_FSL_NUM_LAWS 8
49 #define CONFIG_SYS_FSL_DDRC_GEN1
50 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
52 #elif defined(CONFIG_MPC8541)
53 #define CONFIG_MAX_CPUS 1
54 #define CONFIG_SYS_FSL_NUM_LAWS 8
55 #define CONFIG_SYS_FSL_DDRC_GEN1
56 #define CONFIG_SYS_FSL_SEC_COMPAT 2
57 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
59 #elif defined(CONFIG_MPC8544)
60 #define CONFIG_MAX_CPUS 1
61 #define CONFIG_SYS_FSL_NUM_LAWS 10
62 #define CONFIG_SYS_FSL_DDRC_GEN2
63 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
64 #define CONFIG_SYS_FSL_SEC_COMPAT 2
65 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
66 #define CONFIG_SYS_FSL_ERRATUM_A005125
68 #elif defined(CONFIG_MPC8548)
69 #define CONFIG_MAX_CPUS 1
70 #define CONFIG_SYS_FSL_NUM_LAWS 10
71 #define CONFIG_SYS_FSL_DDRC_GEN2
72 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
73 #define CONFIG_SYS_FSL_SEC_COMPAT 2
74 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
75 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
76 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
77 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
78 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
79 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
80 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
81 #define CONFIG_SYS_FSL_RMU
82 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
83 #define CONFIG_SYS_FSL_ERRATUM_A005125
84 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
85 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
87 #elif defined(CONFIG_MPC8555)
88 #define CONFIG_MAX_CPUS 1
89 #define CONFIG_SYS_FSL_NUM_LAWS 8
90 #define CONFIG_SYS_FSL_DDRC_GEN1
91 #define CONFIG_SYS_FSL_SEC_COMPAT 2
92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
94 #elif defined(CONFIG_MPC8560)
95 #define CONFIG_MAX_CPUS 1
96 #define CONFIG_SYS_FSL_NUM_LAWS 8
97 #define CONFIG_SYS_FSL_DDRC_GEN1
98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
100 #elif defined(CONFIG_MPC8568)
101 #define CONFIG_MAX_CPUS 1
102 #define CONFIG_SYS_FSL_NUM_LAWS 10
103 #define CONFIG_SYS_FSL_DDRC_GEN2
104 #define CONFIG_SYS_FSL_SEC_COMPAT 2
105 #define QE_MURAM_SIZE 0x10000UL
106 #define MAX_QE_RISC 2
107 #define QE_NUM_OF_SNUM 28
108 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
109 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
110 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
111 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
112 #define CONFIG_SYS_FSL_RMU
113 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
115 #elif defined(CONFIG_MPC8569)
116 #define CONFIG_MAX_CPUS 1
117 #define CONFIG_SYS_FSL_NUM_LAWS 10
118 #define CONFIG_SYS_FSL_SEC_COMPAT 2
119 #define QE_MURAM_SIZE 0x20000UL
120 #define MAX_QE_RISC 4
121 #define QE_NUM_OF_SNUM 46
122 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
123 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
124 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
125 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
126 #define CONFIG_SYS_FSL_RMU
127 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
128 #define CONFIG_SYS_FSL_ERRATUM_A004508
129 #define CONFIG_SYS_FSL_ERRATUM_A005125
131 #elif defined(CONFIG_MPC8572)
132 #define CONFIG_MAX_CPUS 2
133 #define CONFIG_SYS_FSL_NUM_LAWS 12
134 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
135 #define CONFIG_SYS_FSL_SEC_COMPAT 2
136 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
137 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
138 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
139 #define CONFIG_SYS_FSL_ERRATUM_A004508
140 #define CONFIG_SYS_FSL_ERRATUM_A005125
142 #elif defined(CONFIG_P1010)
143 #define CONFIG_MAX_CPUS 1
144 #define CONFIG_FSL_SDHC_V2_3
145 #define CONFIG_SYS_FSL_NUM_LAWS 12
146 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
147 #define CONFIG_TSECV2
148 #define CONFIG_SYS_FSL_SEC_COMPAT 4
149 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
150 #define CONFIG_NUM_DDR_CONTROLLERS 1
151 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
152 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
153 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
154 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
155 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
156 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
157 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
158 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
159 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
160 #define CONFIG_SYS_FSL_ERRATUM_A005125
161 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
162 #define CONFIG_SYS_FSL_ERRATUM_A004508
163 #define CONFIG_SYS_FSL_ERRATUM_A007075
164 #define CONFIG_SYS_FSL_ERRATUM_A006261
165 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
166 #define CONFIG_ESDHC_HC_BLK_ADDR
168 /* P1011 is single core version of P1020 */
169 #elif defined(CONFIG_P1011)
170 #define CONFIG_MAX_CPUS 1
171 #define CONFIG_SYS_FSL_NUM_LAWS 12
172 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
173 #define CONFIG_TSECV2
174 #define CONFIG_FSL_PCIE_DISABLE_ASPM
175 #define CONFIG_SYS_FSL_SEC_COMPAT 2
176 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
177 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
178 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
180 #define CONFIG_SYS_FSL_ERRATUM_A004508
181 #define CONFIG_SYS_FSL_ERRATUM_A005125
183 /* P1012 is single core version of P1021 */
184 #elif defined(CONFIG_P1012)
185 #define CONFIG_MAX_CPUS 1
186 #define CONFIG_SYS_FSL_NUM_LAWS 12
187 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
188 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
189 #define CONFIG_TSECV2
190 #define CONFIG_FSL_PCIE_DISABLE_ASPM
191 #define CONFIG_SYS_FSL_SEC_COMPAT 2
192 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
193 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
194 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
195 #define QE_MURAM_SIZE 0x6000UL
196 #define MAX_QE_RISC 1
197 #define QE_NUM_OF_SNUM 28
198 #define CONFIG_SYS_FSL_ERRATUM_A004508
199 #define CONFIG_SYS_FSL_ERRATUM_A005125
201 /* P1013 is single core version of P1022 */
202 #elif defined(CONFIG_P1013)
203 #define CONFIG_MAX_CPUS 1
204 #define CONFIG_SYS_FSL_NUM_LAWS 12
205 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
206 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
207 #define CONFIG_TSECV2
208 #define CONFIG_SYS_FSL_SEC_COMPAT 2
209 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
210 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
212 #define CONFIG_FSL_SATA_ERRATUM_A001
213 #define CONFIG_SYS_FSL_ERRATUM_A004508
214 #define CONFIG_SYS_FSL_ERRATUM_A005125
216 #elif defined(CONFIG_P1014)
217 #define CONFIG_MAX_CPUS 1
218 #define CONFIG_FSL_SDHC_V2_3
219 #define CONFIG_SYS_FSL_NUM_LAWS 12
220 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
221 #define CONFIG_TSECV2
222 #define CONFIG_SYS_FSL_SEC_COMPAT 4
223 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
224 #define CONFIG_NUM_DDR_CONTROLLERS 1
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
227 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
228 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
229 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
230 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
231 #define CONFIG_SYS_FSL_ERRATUM_A004508
233 /* P1017 is single core version of P1023 */
234 #elif defined(CONFIG_P1017)
235 #define CONFIG_MAX_CPUS 1
236 #define CONFIG_SYS_FSL_NUM_LAWS 12
237 #define CONFIG_SYS_FSL_SEC_COMPAT 4
238 #define CONFIG_SYS_NUM_FMAN 1
239 #define CONFIG_SYS_NUM_FM1_DTSEC 2
240 #define CONFIG_NUM_DDR_CONTROLLERS 1
241 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
242 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
243 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
244 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
245 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
247 #define CONFIG_SYS_FSL_ERRATUM_A004508
248 #define CONFIG_SYS_FSL_ERRATUM_A005125
250 #elif defined(CONFIG_P1020)
251 #define CONFIG_MAX_CPUS 2
252 #define CONFIG_SYS_FSL_NUM_LAWS 12
253 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
254 #define CONFIG_TSECV2
255 #define CONFIG_FSL_PCIE_DISABLE_ASPM
256 #define CONFIG_SYS_FSL_SEC_COMPAT 2
257 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
258 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
259 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
260 #define CONFIG_SYS_FSL_ERRATUM_A004508
261 #define CONFIG_SYS_FSL_ERRATUM_A005125
262 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
263 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
266 #elif defined(CONFIG_P1021)
267 #define CONFIG_MAX_CPUS 2
268 #define CONFIG_SYS_FSL_NUM_LAWS 12
269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
270 #define CONFIG_TSECV2
271 #define CONFIG_FSL_PCIE_DISABLE_ASPM
272 #define CONFIG_SYS_FSL_SEC_COMPAT 2
273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
276 #define QE_MURAM_SIZE 0x6000UL
277 #define MAX_QE_RISC 1
278 #define QE_NUM_OF_SNUM 28
279 #define CONFIG_SYS_FSL_ERRATUM_A004508
280 #define CONFIG_SYS_FSL_ERRATUM_A005125
281 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
283 #elif defined(CONFIG_P1022)
284 #define CONFIG_MAX_CPUS 2
285 #define CONFIG_SYS_FSL_NUM_LAWS 12
286 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
287 #define CONFIG_TSECV2
288 #define CONFIG_SYS_FSL_SEC_COMPAT 2
289 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
290 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
291 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
293 #define CONFIG_FSL_SATA_ERRATUM_A001
294 #define CONFIG_SYS_FSL_ERRATUM_A004508
295 #define CONFIG_SYS_FSL_ERRATUM_A005125
297 #elif defined(CONFIG_P1023)
298 #define CONFIG_MAX_CPUS 2
299 #define CONFIG_SYS_FSL_NUM_LAWS 12
300 #define CONFIG_SYS_FSL_SEC_COMPAT 4
301 #define CONFIG_SYS_NUM_FMAN 1
302 #define CONFIG_SYS_NUM_FM1_DTSEC 2
303 #define CONFIG_NUM_DDR_CONTROLLERS 1
304 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
305 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
306 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
307 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
308 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
309 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
310 #define CONFIG_SYS_FSL_ERRATUM_A004508
311 #define CONFIG_SYS_FSL_ERRATUM_A005125
312 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
313 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
315 /* P1024 is lower end variant of P1020 */
316 #elif defined(CONFIG_P1024)
317 #define CONFIG_MAX_CPUS 2
318 #define CONFIG_SYS_FSL_NUM_LAWS 12
319 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
320 #define CONFIG_TSECV2
321 #define CONFIG_FSL_PCIE_DISABLE_ASPM
322 #define CONFIG_SYS_FSL_SEC_COMPAT 2
323 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
324 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
325 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
326 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
327 #define CONFIG_SYS_FSL_ERRATUM_A004508
328 #define CONFIG_SYS_FSL_ERRATUM_A005125
330 /* P1025 is lower end variant of P1021 */
331 #elif defined(CONFIG_P1025)
332 #define CONFIG_MAX_CPUS 2
333 #define CONFIG_SYS_FSL_NUM_LAWS 12
334 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
335 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
336 #define CONFIG_TSECV2
337 #define CONFIG_FSL_PCIE_DISABLE_ASPM
338 #define CONFIG_SYS_FSL_SEC_COMPAT 2
339 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
340 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
341 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
342 #define QE_MURAM_SIZE 0x6000UL
343 #define MAX_QE_RISC 1
344 #define QE_NUM_OF_SNUM 28
345 #define CONFIG_SYS_FSL_ERRATUM_A004508
346 #define CONFIG_SYS_FSL_ERRATUM_A005125
348 /* P2010 is single core version of P2020 */
349 #elif defined(CONFIG_P2010)
350 #define CONFIG_MAX_CPUS 1
351 #define CONFIG_SYS_FSL_NUM_LAWS 12
352 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
353 #define CONFIG_SYS_FSL_SEC_COMPAT 2
354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
355 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
356 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
357 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
358 #define CONFIG_SYS_FSL_ERRATUM_A004508
359 #define CONFIG_SYS_FSL_ERRATUM_A005125
361 #elif defined(CONFIG_P2020)
362 #define CONFIG_MAX_CPUS 2
363 #define CONFIG_SYS_FSL_NUM_LAWS 12
364 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
365 #define CONFIG_SYS_FSL_SEC_COMPAT 2
366 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
367 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
368 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
369 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
370 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
371 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
372 #define CONFIG_SYS_FSL_RMU
373 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
374 #define CONFIG_SYS_FSL_ERRATUM_A004508
375 #define CONFIG_SYS_FSL_ERRATUM_A005125
376 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
378 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
379 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
380 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
381 #define CONFIG_MAX_CPUS 4
382 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
383 #define CONFIG_SYS_FSL_NUM_LAWS 32
384 #define CONFIG_SYS_FSL_SEC_COMPAT 4
385 #define CONFIG_SYS_NUM_FMAN 1
386 #define CONFIG_SYS_NUM_FM1_DTSEC 5
387 #define CONFIG_SYS_NUM_FM1_10GEC 1
388 #define CONFIG_NUM_DDR_CONTROLLERS 1
389 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
390 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
391 #define CONFIG_SYS_FSL_TBCLK_DIV 32
392 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
393 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
394 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
395 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
396 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
397 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
398 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
399 #define CONFIG_SYS_FSL_ERRATUM_USB14
400 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
401 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
402 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
403 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
404 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
405 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
406 #define CONFIG_SYS_FSL_ERRATUM_A004510
407 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
408 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
409 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
410 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
411 #define CONFIG_SYS_FSL_ERRATUM_A004849
412 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
413 #define CONFIG_SYS_FSL_ERRATUM_A006261
414 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
416 #elif defined(CONFIG_PPC_P3041)
417 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
418 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
419 #define CONFIG_MAX_CPUS 4
420 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
421 #define CONFIG_SYS_FSL_NUM_LAWS 32
422 #define CONFIG_SYS_FSL_SEC_COMPAT 4
423 #define CONFIG_SYS_NUM_FMAN 1
424 #define CONFIG_SYS_NUM_FM1_DTSEC 5
425 #define CONFIG_SYS_NUM_FM1_10GEC 1
426 #define CONFIG_NUM_DDR_CONTROLLERS 1
427 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
428 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
429 #define CONFIG_SYS_FSL_TBCLK_DIV 32
430 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
431 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
432 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
433 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
434 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
435 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
436 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
437 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
438 #define CONFIG_SYS_FSL_ERRATUM_USB14
439 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
440 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
441 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
442 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
443 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
444 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
445 #define CONFIG_SYS_FSL_ERRATUM_A004510
446 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
447 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
448 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
449 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
450 #define CONFIG_SYS_FSL_ERRATUM_A004849
451 #define CONFIG_SYS_FSL_ERRATUM_A005812
452 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
453 #define CONFIG_SYS_FSL_ERRATUM_A006261
454 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
456 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
457 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
458 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
459 #define CONFIG_MAX_CPUS 8
460 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
461 #define CONFIG_SYS_FSL_NUM_LAWS 32
462 #define CONFIG_SYS_FSL_SEC_COMPAT 4
463 #define CONFIG_SYS_NUM_FMAN 2
464 #define CONFIG_SYS_NUM_FM1_DTSEC 4
465 #define CONFIG_SYS_NUM_FM2_DTSEC 4
466 #define CONFIG_SYS_NUM_FM1_10GEC 1
467 #define CONFIG_SYS_NUM_FM2_10GEC 1
468 #define CONFIG_NUM_DDR_CONTROLLERS 2
469 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
470 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
471 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
472 #define CONFIG_SYS_FSL_TBCLK_DIV 16
473 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
474 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
475 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
476 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
477 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
478 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
479 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
480 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
481 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
482 #define CONFIG_SYS_P4080_ERRATUM_CPU22
483 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
484 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
485 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
486 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
487 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
488 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
489 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
490 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
491 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
492 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
493 #define CONFIG_SYS_FSL_RMU
494 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
495 #define CONFIG_SYS_FSL_ERRATUM_A004510
496 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
497 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
498 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
499 #define CONFIG_SYS_FSL_ERRATUM_A004849
500 #define CONFIG_SYS_FSL_ERRATUM_A004580
501 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
502 #define CONFIG_SYS_FSL_ERRATUM_A005812
503 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
504 #define CONFIG_SYS_FSL_ERRATUM_A007075
505 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
507 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
508 #define CONFIG_SYS_PPC64 /* 64-bit core */
509 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
510 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
511 #define CONFIG_MAX_CPUS 2
512 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
513 #define CONFIG_SYS_FSL_NUM_LAWS 32
514 #define CONFIG_SYS_FSL_SEC_COMPAT 4
515 #define CONFIG_SYS_NUM_FMAN 1
516 #define CONFIG_SYS_NUM_FM1_DTSEC 5
517 #define CONFIG_SYS_NUM_FM1_10GEC 1
518 #define CONFIG_NUM_DDR_CONTROLLERS 2
519 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
520 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
521 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
522 #define CONFIG_SYS_FSL_TBCLK_DIV 32
523 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
524 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
525 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
526 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
527 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
528 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
529 #define CONFIG_SYS_FSL_ERRATUM_USB14
530 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
531 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
532 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
533 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
534 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
535 #define CONFIG_SYS_FSL_ERRATUM_A004510
536 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
537 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
538 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
539 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
540 #define CONFIG_SYS_FSL_ERRATUM_A006261
541 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
543 #elif defined(CONFIG_PPC_P5040)
544 #define CONFIG_SYS_PPC64
545 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
546 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
547 #define CONFIG_MAX_CPUS 4
548 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
549 #define CONFIG_SYS_FSL_NUM_LAWS 32
550 #define CONFIG_SYS_FSL_SEC_COMPAT 4
551 #define CONFIG_SYS_NUM_FMAN 2
552 #define CONFIG_SYS_NUM_FM1_DTSEC 5
553 #define CONFIG_SYS_NUM_FM1_10GEC 1
554 #define CONFIG_SYS_NUM_FM2_DTSEC 5
555 #define CONFIG_SYS_NUM_FM2_10GEC 1
556 #define CONFIG_NUM_DDR_CONTROLLERS 2
557 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
558 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
559 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
560 #define CONFIG_SYS_FSL_TBCLK_DIV 16
561 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
562 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
563 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
564 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
565 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
566 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
567 #define CONFIG_SYS_FSL_ERRATUM_USB14
568 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
569 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
570 #define CONFIG_SYS_FSL_ERRATUM_A004699
571 #define CONFIG_SYS_FSL_ERRATUM_A004510
572 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
573 #define CONFIG_SYS_FSL_ERRATUM_A006261
574 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
575 #define CONFIG_SYS_FSL_ERRATUM_A005812
577 #elif defined(CONFIG_BSC9131)
578 #define CONFIG_MAX_CPUS 1
579 #define CONFIG_FSL_SDHC_V2_3
580 #define CONFIG_SYS_FSL_NUM_LAWS 12
581 #define CONFIG_TSECV2
582 #define CONFIG_SYS_FSL_SEC_COMPAT 4
583 #define CONFIG_NUM_DDR_CONTROLLERS 1
584 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
585 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
586 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
587 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
588 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
589 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
590 #define CONFIG_NAND_FSL_IFC
591 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
592 #define CONFIG_SYS_FSL_ERRATUM_A005125
593 #define CONFIG_ESDHC_HC_BLK_ADDR
595 #elif defined(CONFIG_BSC9132)
596 #define CONFIG_MAX_CPUS 2
597 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
598 #define CONFIG_FSL_SDHC_V2_3
599 #define CONFIG_SYS_FSL_NUM_LAWS 12
600 #define CONFIG_TSECV2
601 #define CONFIG_SYS_FSL_SEC_COMPAT 4
602 #define CONFIG_NUM_DDR_CONTROLLERS 2
603 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
604 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
605 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
606 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
607 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
608 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
609 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
610 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
611 #define CONFIG_NAND_FSL_IFC
612 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
613 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
614 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
615 #define CONFIG_SYS_FSL_ERRATUM_A005125
616 #define CONFIG_SYS_FSL_ERRATUM_A005434
617 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
618 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
619 #define CONFIG_ESDHC_HC_BLK_ADDR
621 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
622 defined(CONFIG_PPC_T4080)
624 #define CONFIG_SYS_PPC64 /* 64-bit core */
625 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
626 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
627 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
628 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
629 #ifdef CONFIG_PPC_T4240
630 #define CONFIG_MAX_CPUS 12
631 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
632 #define CONFIG_SYS_NUM_FM1_DTSEC 8
633 #define CONFIG_SYS_NUM_FM1_10GEC 2
634 #define CONFIG_SYS_NUM_FM2_DTSEC 8
635 #define CONFIG_SYS_NUM_FM2_10GEC 2
636 #define CONFIG_NUM_DDR_CONTROLLERS 3
638 #define CONFIG_SYS_NUM_FM1_DTSEC 6
639 #define CONFIG_SYS_NUM_FM1_10GEC 1
640 #define CONFIG_SYS_NUM_FM2_DTSEC 8
641 #define CONFIG_SYS_NUM_FM2_10GEC 1
642 #define CONFIG_NUM_DDR_CONTROLLERS 2
643 #if defined(CONFIG_PPC_T4160)
644 #define CONFIG_MAX_CPUS 8
645 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
646 #elif defined(CONFIG_PPC_T4080)
647 #define CONFIG_MAX_CPUS 4
648 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
651 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
652 #define CONFIG_SYS_FSL_NUM_LAWS 32
653 #define CONFIG_SYS_FSL_SRDS_1
654 #define CONFIG_SYS_FSL_SRDS_2
655 #define CONFIG_SYS_FSL_SRDS_3
656 #define CONFIG_SYS_FSL_SRDS_4
657 #define CONFIG_SYS_FSL_SEC_COMPAT 4
658 #define CONFIG_SYS_NUM_FMAN 2
659 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
660 #define CONFIG_SYS_PME_CLK 0
661 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
662 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
663 #define CONFIG_SYS_FMAN_V3
664 #define CONFIG_SYS_FM1_CLK 3
665 #define CONFIG_SYS_FM2_CLK 3
666 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
667 #define CONFIG_SYS_FSL_TBCLK_DIV 16
668 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
669 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
670 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
671 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
672 #define CONFIG_SYS_FSL_SRIO_LIODN
673 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
674 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
675 #define CONFIG_SYS_FSL_ERRATUM_A004468
676 #define CONFIG_SYS_FSL_ERRATUM_A_004934
677 #define CONFIG_SYS_FSL_ERRATUM_A005871
678 #define CONFIG_SYS_FSL_ERRATUM_A006261
679 #define CONFIG_SYS_FSL_ERRATUM_A006379
680 #define CONFIG_SYS_FSL_ERRATUM_A007186
681 #define CONFIG_SYS_FSL_ERRATUM_A006593
682 #define CONFIG_SYS_FSL_ERRATUM_A007798
683 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
684 #define CONFIG_SYS_FSL_SFP_VER_3_0
685 #define CONFIG_SYS_FSL_PCI_VER_3_X
687 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
689 #define CONFIG_SYS_PPC64 /* 64-bit core */
690 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
691 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
692 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
693 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
694 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
695 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
696 #define CONFIG_SYS_FSL_NUM_LAWS 32
697 #define CONFIG_SYS_FSL_SRDS_1
698 #define CONFIG_SYS_FSL_SRDS_2
699 #define CONFIG_SYS_MAPLE
700 #define CONFIG_SYS_CPRI
701 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
702 #define CONFIG_SYS_FSL_SEC_COMPAT 4
703 #define CONFIG_SYS_NUM_FMAN 1
704 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
705 #define CONFIG_SYS_FM1_CLK 0
706 #define CONFIG_SYS_CPRI_CLK 3
707 #define CONFIG_SYS_ULB_CLK 4
708 #define CONFIG_SYS_ETVPE_CLK 1
709 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
710 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
711 #define CONFIG_SYS_FMAN_V3
712 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
713 #define CONFIG_SYS_FSL_TBCLK_DIV 16
714 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
715 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
716 #define CONFIG_SYS_FSL_ERRATUM_A_004934
717 #define CONFIG_SYS_FSL_ERRATUM_A005871
718 #define CONFIG_SYS_FSL_ERRATUM_A006379
719 #define CONFIG_SYS_FSL_ERRATUM_A007186
720 #define CONFIG_SYS_FSL_ERRATUM_A006593
721 #define CONFIG_SYS_FSL_ERRATUM_A007075
722 #define CONFIG_SYS_FSL_ERRATUM_A006475
723 #define CONFIG_SYS_FSL_ERRATUM_A006384
724 #define CONFIG_SYS_FSL_ERRATUM_A007212
725 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
726 #define CONFIG_SYS_FSL_SFP_VER_3_0
728 #ifdef CONFIG_PPC_B4860
729 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
730 #define CONFIG_MAX_CPUS 4
731 #define CONFIG_MAX_DSP_CPUS 12
732 #define CONFIG_NUM_DSP_CPUS 6
733 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
734 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
735 #define CONFIG_SYS_NUM_FM1_DTSEC 6
736 #define CONFIG_SYS_NUM_FM1_10GEC 2
737 #define CONFIG_NUM_DDR_CONTROLLERS 2
738 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
739 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
740 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
741 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
742 #define CONFIG_SYS_FSL_SRIO_LIODN
744 #define CONFIG_MAX_CPUS 2
745 #define CONFIG_MAX_DSP_CPUS 2
746 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
747 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
748 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
749 #define CONFIG_SYS_NUM_FM1_DTSEC 4
750 #define CONFIG_SYS_NUM_FM1_10GEC 0
751 #define CONFIG_NUM_DDR_CONTROLLERS 1
754 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
755 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
757 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
758 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
759 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
760 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
761 #ifdef CONFIG_SYS_FSL_DDR4
762 #define CONFIG_SYS_FSL_DDRC_GEN4
764 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
765 #define CONFIG_MAX_CPUS 4
766 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
767 #define CONFIG_MAX_CPUS 2
769 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
770 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
771 #define CONFIG_SYS_SDHC_CLOCK 0
772 #define CONFIG_SYS_FSL_NUM_LAWS 16
773 #define CONFIG_SYS_FSL_SRDS_1
774 #define CONFIG_SYS_FSL_SEC_COMPAT 5
775 #define CONFIG_SYS_NUM_FMAN 1
776 #define CONFIG_SYS_NUM_FM1_DTSEC 5
777 #define CONFIG_NUM_DDR_CONTROLLERS 1
778 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
779 #define CONFIG_PME_PLAT_CLK_DIV 2
780 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
781 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
782 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
783 #define CONFIG_SYS_FSL_ERRATUM_A008044
784 #define CONFIG_SYS_FMAN_V3
785 #define CONFIG_FM_PLAT_CLK_DIV 1
786 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
787 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
788 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
789 #define CONFIG_SYS_FSL_TBCLK_DIV 16
790 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
791 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
792 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
793 #define CONFIG_SYS_FSL_ERRATUM_A006261
794 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
795 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
796 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
797 #define QE_MURAM_SIZE 0x6000UL
798 #define MAX_QE_RISC 1
799 #define QE_NUM_OF_SNUM 28
801 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
802 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
804 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
805 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
806 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
807 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
808 #define CONFIG_SYS_FMAN_V3
809 #ifdef CONFIG_SYS_FSL_DDR4
810 #define CONFIG_SYS_FSL_DDRC_GEN4
812 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
813 #define CONFIG_MAX_CPUS 2
814 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
815 #define CONFIG_MAX_CPUS 1
817 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
818 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
819 #define CONFIG_SYS_SDHC_CLOCK 0
820 #define CONFIG_SYS_FSL_NUM_LAWS 16
821 #define CONFIG_SYS_FSL_SRDS_1
822 #define CONFIG_SYS_FSL_SEC_COMPAT 5
823 #define CONFIG_SYS_NUM_FMAN 1
824 #define CONFIG_SYS_NUM_FM1_DTSEC 4
825 #define CONFIG_SYS_NUM_FM1_10GEC 1
826 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
827 #define CONFIG_NUM_DDR_CONTROLLERS 1
828 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
829 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
830 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
831 #define CONFIG_SYS_FM1_CLK 0
832 #define CONFIG_QBMAN_CLK_DIV 1
833 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
834 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
835 #define CONFIG_SYS_FSL_TBCLK_DIV 16
836 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
837 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
838 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
839 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
840 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
841 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
842 #define QE_MURAM_SIZE 0x6000UL
843 #define MAX_QE_RISC 1
844 #define QE_NUM_OF_SNUM 28
845 #define CONFIG_SYS_FSL_SFP_VER_3_0
847 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
849 #define CONFIG_SYS_PPC64 /* 64-bit core */
850 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
851 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
852 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
853 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
854 #define CONFIG_SYS_FSL_QMAN_V3
855 #define CONFIG_MAX_CPUS 4
856 #define CONFIG_SYS_FSL_NUM_LAWS 32
857 #define CONFIG_SYS_FSL_SEC_COMPAT 4
858 #define CONFIG_SYS_NUM_FMAN 1
859 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
860 #define CONFIG_SYS_FSL_SRDS_1
861 #define CONFIG_SYS_FSL_PCI_VER_3_X
862 #if defined(CONFIG_PPC_T2080)
863 #define CONFIG_SYS_NUM_FM1_DTSEC 8
864 #define CONFIG_SYS_NUM_FM1_10GEC 4
865 #define CONFIG_SYS_FSL_SRDS_2
866 #define CONFIG_SYS_FSL_SRIO_LIODN
867 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
868 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
869 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
870 #elif defined(CONFIG_PPC_T2081)
871 #define CONFIG_SYS_NUM_FM1_DTSEC 6
872 #define CONFIG_SYS_NUM_FM1_10GEC 2
874 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
875 #define CONFIG_NUM_DDR_CONTROLLERS 1
876 #define CONFIG_PME_PLAT_CLK_DIV 1
877 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
878 #define CONFIG_SYS_FM1_CLK 0
879 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
880 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
881 #define CONFIG_SYS_FMAN_V3
882 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
883 #define CONFIG_SYS_FSL_TBCLK_DIV 16
884 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
885 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
886 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
887 #define CONFIG_SYS_FSL_ERRATUM_A007212
888 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
889 #define CONFIG_SYS_FSL_SFP_VER_3_0
890 #define CONFIG_SYS_FSL_ISBC_VER 2
891 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
892 #define CONFIG_SYS_FSL_ERRATUM_A006261
893 #define CONFIG_SYS_FSL_ERRATUM_A006593
894 #define CONFIG_SYS_FSL_ERRATUM_A007186
895 #define CONFIG_SYS_FSL_ERRATUM_A006379
896 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
897 #define CONFIG_SYS_FSL_SFP_VER_3_0
900 #elif defined(CONFIG_PPC_C29X)
901 #define CONFIG_MAX_CPUS 1
902 #define CONFIG_FSL_SDHC_V2_3
903 #define CONFIG_SYS_FSL_NUM_LAWS 12
904 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
905 #define CONFIG_TSECV2_1
906 #define CONFIG_SYS_FSL_SEC_COMPAT 6
907 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
908 #define CONFIG_NUM_DDR_CONTROLLERS 1
909 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
910 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
911 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
912 #define CONFIG_SYS_FSL_ERRATUM_A005125
914 #elif defined(CONFIG_QEMU_E500)
915 #define CONFIG_MAX_CPUS 1
916 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
919 #error Processor type not defined for this platform
922 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
923 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
927 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
929 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
932 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
933 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
934 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
935 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
936 #define CONFIG_SYS_FSL_DDRC_GEN3
939 #endif /* _ASM_MPC85xx_CONFIG_H_ */