2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 /* Number of TLB CAM entries we have on FSL Book-E chips */
27 #if defined(CONFIG_E500MC)
28 #define CONFIG_SYS_NUM_TLBCAMS 64
29 #elif defined(CONFIG_E500)
30 #define CONFIG_SYS_NUM_TLBCAMS 16
33 #if defined(CONFIG_MPC8536)
34 #define CONFIG_MAX_CPUS 1
35 #define CONFIG_SYS_FSL_NUM_LAWS 12
36 #define CONFIG_SYS_FSL_SEC_COMPAT 2
38 #elif defined(CONFIG_MPC8540)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 8
42 #elif defined(CONFIG_MPC8541)
43 #define CONFIG_MAX_CPUS 1
44 #define CONFIG_SYS_FSL_NUM_LAWS 8
45 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #elif defined(CONFIG_MPC8544)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 10
50 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #elif defined(CONFIG_MPC8548)
53 #define CONFIG_MAX_CPUS 1
54 #define CONFIG_SYS_FSL_NUM_LAWS 10
55 #define CONFIG_SYS_FSL_SEC_COMPAT 2
57 #elif defined(CONFIG_MPC8555)
58 #define CONFIG_MAX_CPUS 1
59 #define CONFIG_SYS_FSL_NUM_LAWS 8
60 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #elif defined(CONFIG_MPC8560)
63 #define CONFIG_MAX_CPUS 1
64 #define CONFIG_SYS_FSL_NUM_LAWS 8
66 #elif defined(CONFIG_MPC8568)
67 #define CONFIG_MAX_CPUS 1
68 #define CONFIG_SYS_FSL_NUM_LAWS 10
69 #define CONFIG_SYS_FSL_SEC_COMPAT 2
70 #define QE_MURAM_SIZE 0x10000UL
72 #define QE_NUM_OF_SNUM 28
74 #elif defined(CONFIG_MPC8569)
75 #define CONFIG_MAX_CPUS 1
76 #define CONFIG_SYS_FSL_NUM_LAWS 10
77 #define CONFIG_SYS_FSL_SEC_COMPAT 2
78 #define QE_MURAM_SIZE 0x20000UL
80 #define QE_NUM_OF_SNUM 46
82 #elif defined(CONFIG_MPC8572)
83 #define CONFIG_MAX_CPUS 2
84 #define CONFIG_SYS_FSL_NUM_LAWS 12
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
89 #elif defined(CONFIG_P1010)
90 #define CONFIG_MAX_CPUS 1
91 #define CONFIG_SYS_FSL_NUM_LAWS 12
93 #define CONFIG_SYS_FSL_SEC_COMPAT 4
94 #define CONFIG_FSL_SATA_V2
95 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
96 #define CONFIG_NUM_DDR_CONTROLLERS 1
97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
99 /* P1011 is single core version of P1020 */
100 #elif defined(CONFIG_P1011)
101 #define CONFIG_MAX_CPUS 1
102 #define CONFIG_SYS_FSL_NUM_LAWS 12
103 #define CONFIG_TSECV2
104 #define CONFIG_FSL_PCIE_DISABLE_ASPM
105 #define CONFIG_SYS_FSL_SEC_COMPAT 2
106 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
107 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
109 /* P1012 is single core version of P1021 */
110 #elif defined(CONFIG_P1012)
111 #define CONFIG_MAX_CPUS 1
112 #define CONFIG_SYS_FSL_NUM_LAWS 12
113 #define CONFIG_TSECV2
114 #define CONFIG_FSL_PCIE_DISABLE_ASPM
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
117 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
118 #define QE_MURAM_SIZE 0x6000UL
119 #define MAX_QE_RISC 1
120 #define QE_NUM_OF_SNUM 28
122 /* P1013 is single core version of P1022 */
123 #elif defined(CONFIG_P1013)
124 #define CONFIG_MAX_CPUS 1
125 #define CONFIG_SYS_FSL_NUM_LAWS 12
126 #define CONFIG_TSECV2
127 #define CONFIG_SYS_FSL_SEC_COMPAT 2
128 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
129 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
130 #define CONFIG_FSL_SATA_ERRATUM_A001
132 #elif defined(CONFIG_P1014)
133 #define CONFIG_MAX_CPUS 1
134 #define CONFIG_SYS_FSL_NUM_LAWS 12
135 #define CONFIG_TSECV2
136 #define CONFIG_SYS_FSL_SEC_COMPAT 4
137 #define CONFIG_FSL_SATA_V2
138 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
139 #define CONFIG_NUM_DDR_CONTROLLERS 1
140 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
142 /* P1015 is single core version of P1024 */
143 #elif defined(CONFIG_P1015)
144 #define CONFIG_MAX_CPUS 1
145 #define CONFIG_SYS_FSL_NUM_LAWS 12
146 #define CONFIG_TSECV2
147 #define CONFIG_FSL_PCIE_DISABLE_ASPM
148 #define CONFIG_SYS_FSL_SEC_COMPAT 2
149 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
152 /* P1016 is single core version of P1025 */
153 #elif defined(CONFIG_P1016)
154 #define CONFIG_MAX_CPUS 1
155 #define CONFIG_SYS_FSL_NUM_LAWS 12
156 #define CONFIG_TSECV2
157 #define CONFIG_FSL_PCIE_DISABLE_ASPM
158 #define CONFIG_SYS_FSL_SEC_COMPAT 2
159 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
161 #define QE_MURAM_SIZE 0x6000UL
162 #define MAX_QE_RISC 1
163 #define QE_NUM_OF_SNUM 28
165 /* P1017 is single core version of P1023 */
166 #elif defined(CONFIG_P1017)
167 #define CONFIG_MAX_CPUS 1
168 #define CONFIG_SYS_FSL_NUM_LAWS 12
169 #define CONFIG_SYS_FSL_SEC_COMPAT 4
170 #define CONFIG_SYS_NUM_FMAN 1
171 #define CONFIG_SYS_NUM_FM1_DTSEC 2
172 #define CONFIG_NUM_DDR_CONTROLLERS 1
173 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
174 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
175 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
177 #elif defined(CONFIG_P1020)
178 #define CONFIG_MAX_CPUS 2
179 #define CONFIG_SYS_FSL_NUM_LAWS 12
180 #define CONFIG_TSECV2
181 #define CONFIG_FSL_PCIE_DISABLE_ASPM
182 #define CONFIG_SYS_FSL_SEC_COMPAT 2
183 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
184 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186 #elif defined(CONFIG_P1021)
187 #define CONFIG_MAX_CPUS 2
188 #define CONFIG_SYS_FSL_NUM_LAWS 12
189 #define CONFIG_TSECV2
190 #define CONFIG_FSL_PCIE_DISABLE_ASPM
191 #define CONFIG_SYS_FSL_SEC_COMPAT 2
192 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
193 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
194 #define QE_MURAM_SIZE 0x6000UL
195 #define MAX_QE_RISC 1
196 #define QE_NUM_OF_SNUM 28
198 #elif defined(CONFIG_P1022)
199 #define CONFIG_MAX_CPUS 2
200 #define CONFIG_SYS_FSL_NUM_LAWS 12
201 #define CONFIG_TSECV2
202 #define CONFIG_SYS_FSL_SEC_COMPAT 2
203 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
204 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
205 #define CONFIG_FSL_SATA_ERRATUM_A001
207 #elif defined(CONFIG_P1023)
208 #define CONFIG_MAX_CPUS 2
209 #define CONFIG_SYS_FSL_NUM_LAWS 12
210 #define CONFIG_SYS_FSL_SEC_COMPAT 4
211 #define CONFIG_SYS_NUM_FMAN 1
212 #define CONFIG_SYS_NUM_FM1_DTSEC 2
213 #define CONFIG_NUM_DDR_CONTROLLERS 1
214 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
215 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
216 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
218 /* P1024 is lower end variant of P1020 */
219 #elif defined(CONFIG_P1024)
220 #define CONFIG_MAX_CPUS 2
221 #define CONFIG_SYS_FSL_NUM_LAWS 12
222 #define CONFIG_TSECV2
223 #define CONFIG_FSL_PCIE_DISABLE_ASPM
224 #define CONFIG_SYS_FSL_SEC_COMPAT 2
225 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
226 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
228 /* P1025 is lower end variant of P1021 */
229 #elif defined(CONFIG_P1025)
230 #define CONFIG_MAX_CPUS 2
231 #define CONFIG_SYS_FSL_NUM_LAWS 12
232 #define CONFIG_TSECV2
233 #define CONFIG_FSL_PCIE_DISABLE_ASPM
234 #define CONFIG_SYS_FSL_SEC_COMPAT 2
235 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
236 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
237 #define QE_MURAM_SIZE 0x6000UL
238 #define MAX_QE_RISC 1
239 #define QE_NUM_OF_SNUM 28
241 /* P2010 is single core version of P2020 */
242 #elif defined(CONFIG_P2010)
243 #define CONFIG_MAX_CPUS 1
244 #define CONFIG_SYS_FSL_NUM_LAWS 12
245 #define CONFIG_SYS_FSL_SEC_COMPAT 2
246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
249 #elif defined(CONFIG_P2020)
250 #define CONFIG_MAX_CPUS 2
251 #define CONFIG_SYS_FSL_NUM_LAWS 12
252 #define CONFIG_SYS_FSL_SEC_COMPAT 2
253 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
254 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
256 #elif defined(CONFIG_PPC_P2040)
257 #define CONFIG_MAX_CPUS 4
258 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
259 #define CONFIG_SYS_FSL_NUM_LAWS 32
260 #define CONFIG_SYS_FSL_SEC_COMPAT 4
261 #define CONFIG_SYS_NUM_FMAN 1
262 #define CONFIG_SYS_NUM_FM1_DTSEC 5
263 #define CONFIG_NUM_DDR_CONTROLLERS 1
264 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
266 #elif defined(CONFIG_PPC_P3041)
267 #define CONFIG_MAX_CPUS 4
268 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
269 #define CONFIG_SYS_FSL_NUM_LAWS 32
270 #define CONFIG_SYS_FSL_SEC_COMPAT 4
271 #define CONFIG_SYS_NUM_FMAN 1
272 #define CONFIG_SYS_NUM_FM1_DTSEC 5
273 #define CONFIG_SYS_NUM_FM1_10GEC 1
274 #define CONFIG_NUM_DDR_CONTROLLERS 1
275 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
277 #elif defined(CONFIG_PPC_P4040)
278 #define CONFIG_MAX_CPUS 4
279 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
280 #define CONFIG_SYS_FSL_NUM_LAWS 32
281 #define CONFIG_SYS_FSL_SEC_COMPAT 4
282 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
284 #elif defined(CONFIG_PPC_P4080)
285 #define CONFIG_MAX_CPUS 8
286 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
287 #define CONFIG_SYS_FSL_NUM_LAWS 32
288 #define CONFIG_SYS_FSL_SEC_COMPAT 4
289 #define CONFIG_SYS_NUM_FMAN 2
290 #define CONFIG_SYS_NUM_FM1_DTSEC 4
291 #define CONFIG_SYS_NUM_FM2_DTSEC 4
292 #define CONFIG_SYS_NUM_FM1_10GEC 1
293 #define CONFIG_SYS_NUM_FM2_10GEC 1
294 #define CONFIG_NUM_DDR_CONTROLLERS 2
295 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
296 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
297 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
298 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
299 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
300 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
301 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
302 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
303 #define CONFIG_SYS_P4080_ERRATUM_CPU22
304 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
306 /* P5010 is single core version of P5020 */
307 #elif defined(CONFIG_PPC_P5010)
308 #define CONFIG_MAX_CPUS 1
309 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
310 #define CONFIG_SYS_FSL_NUM_LAWS 32
311 #define CONFIG_SYS_FSL_SEC_COMPAT 4
312 #define CONFIG_SYS_NUM_FMAN 1
313 #define CONFIG_SYS_NUM_FM1_DTSEC 5
314 #define CONFIG_SYS_NUM_FM1_10GEC 1
315 #define CONFIG_NUM_DDR_CONTROLLERS 1
316 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
318 #elif defined(CONFIG_PPC_P5020)
319 #define CONFIG_MAX_CPUS 2
320 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
321 #define CONFIG_SYS_FSL_NUM_LAWS 32
322 #define CONFIG_SYS_FSL_SEC_COMPAT 4
323 #define CONFIG_SYS_NUM_FMAN 1
324 #define CONFIG_SYS_NUM_FM1_DTSEC 5
325 #define CONFIG_SYS_NUM_FM1_10GEC 1
326 #define CONFIG_NUM_DDR_CONTROLLERS 2
327 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
330 #error Processor type not defined for this platform
333 #endif /* _ASM_MPC85xx_CONFIG_H_ */