2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
21 #define CONFIG_SYS_FSL_IFC_BE
22 #define CONFIG_SYS_FSL_SFP_BE
23 #define CONFIG_SYS_FSL_SEC_MON_BE
25 #if defined(CONFIG_ARCH_MPC8536)
26 #define CONFIG_SYS_FSL_ERRATUM_A004508
27 #define CONFIG_SYS_FSL_ERRATUM_A005125
29 #elif defined(CONFIG_ARCH_MPC8540)
31 #elif defined(CONFIG_ARCH_MPC8541)
33 #elif defined(CONFIG_ARCH_MPC8544)
34 #define CONFIG_SYS_FSL_ERRATUM_A005125
36 #elif defined(CONFIG_ARCH_MPC8548)
37 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
38 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
39 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
40 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
41 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
42 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
43 #define CONFIG_SYS_FSL_RMU
44 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
45 #define CONFIG_SYS_FSL_ERRATUM_A005125
46 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
47 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
49 #elif defined(CONFIG_ARCH_MPC8555)
51 #elif defined(CONFIG_ARCH_MPC8560)
53 #elif defined(CONFIG_ARCH_MPC8568)
54 #define QE_MURAM_SIZE 0x10000UL
56 #define QE_NUM_OF_SNUM 28
57 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
58 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
59 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
60 #define CONFIG_SYS_FSL_RMU
61 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
63 #elif defined(CONFIG_ARCH_MPC8569)
64 #define QE_MURAM_SIZE 0x20000UL
66 #define QE_NUM_OF_SNUM 46
67 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
68 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
69 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
70 #define CONFIG_SYS_FSL_RMU
71 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
72 #define CONFIG_SYS_FSL_ERRATUM_A004508
73 #define CONFIG_SYS_FSL_ERRATUM_A005125
75 #elif defined(CONFIG_ARCH_MPC8572)
76 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
77 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
78 #define CONFIG_SYS_FSL_ERRATUM_A004508
79 #define CONFIG_SYS_FSL_ERRATUM_A005125
81 #elif defined(CONFIG_ARCH_P1010)
82 #define CONFIG_FSL_SDHC_V2_3
84 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
85 #define CONFIG_NUM_DDR_CONTROLLERS 1
86 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
87 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
88 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
89 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
90 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
91 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
92 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
93 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
94 #define CONFIG_SYS_FSL_ERRATUM_A005125
95 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
96 #define CONFIG_SYS_FSL_ERRATUM_A004508
97 #define CONFIG_SYS_FSL_ERRATUM_A007075
98 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
99 #define CONFIG_SYS_FSL_ERRATUM_A006261
100 #define CONFIG_SYS_FSL_ERRATUM_A004477
101 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
102 #define CONFIG_ESDHC_HC_BLK_ADDR
104 /* P1011 is single core version of P1020 */
105 #elif defined(CONFIG_ARCH_P1011)
106 #define CONFIG_TSECV2
107 #define CONFIG_FSL_PCIE_DISABLE_ASPM
108 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
109 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
111 #define CONFIG_SYS_FSL_ERRATUM_A004508
112 #define CONFIG_SYS_FSL_ERRATUM_A005125
114 #elif defined(CONFIG_ARCH_P1020)
115 #define CONFIG_TSECV2
116 #define CONFIG_FSL_PCIE_DISABLE_ASPM
117 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
118 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
119 #define CONFIG_SYS_FSL_ERRATUM_A004508
120 #define CONFIG_SYS_FSL_ERRATUM_A005125
121 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
122 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
125 #elif defined(CONFIG_ARCH_P1021)
126 #define CONFIG_TSECV2
127 #define CONFIG_FSL_PCIE_DISABLE_ASPM
128 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
129 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
130 #define QE_MURAM_SIZE 0x6000UL
131 #define MAX_QE_RISC 1
132 #define QE_NUM_OF_SNUM 28
133 #define CONFIG_SYS_FSL_ERRATUM_A004508
134 #define CONFIG_SYS_FSL_ERRATUM_A005125
135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
137 #elif defined(CONFIG_ARCH_P1022)
138 #define CONFIG_TSECV2
139 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
140 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142 #define CONFIG_FSL_SATA_ERRATUM_A001
143 #define CONFIG_SYS_FSL_ERRATUM_A004508
144 #define CONFIG_SYS_FSL_ERRATUM_A005125
145 #define CONFIG_SYS_FSL_ERRATUM_A004477
147 #elif defined(CONFIG_ARCH_P1023)
148 #define CONFIG_SYS_NUM_FMAN 1
149 #define CONFIG_SYS_NUM_FM1_DTSEC 2
150 #define CONFIG_NUM_DDR_CONTROLLERS 1
151 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
152 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
153 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
154 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
156 #define CONFIG_SYS_FSL_ERRATUM_A004508
157 #define CONFIG_SYS_FSL_ERRATUM_A005125
158 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
159 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
161 /* P1024 is lower end variant of P1020 */
162 #elif defined(CONFIG_ARCH_P1024)
163 #define CONFIG_TSECV2
164 #define CONFIG_FSL_PCIE_DISABLE_ASPM
165 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
166 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
167 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
168 #define CONFIG_SYS_FSL_ERRATUM_A004508
169 #define CONFIG_SYS_FSL_ERRATUM_A005125
171 /* P1025 is lower end variant of P1021 */
172 #elif defined(CONFIG_ARCH_P1025)
173 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
174 #define CONFIG_TSECV2
175 #define CONFIG_FSL_PCIE_DISABLE_ASPM
176 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
177 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
178 #define QE_MURAM_SIZE 0x6000UL
179 #define MAX_QE_RISC 1
180 #define QE_NUM_OF_SNUM 28
181 #define CONFIG_SYS_FSL_ERRATUM_A004508
182 #define CONFIG_SYS_FSL_ERRATUM_A005125
184 #elif defined(CONFIG_ARCH_P2020)
185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
187 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
188 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
189 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
190 #define CONFIG_SYS_FSL_RMU
191 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
192 #define CONFIG_SYS_FSL_ERRATUM_A004508
193 #define CONFIG_SYS_FSL_ERRATUM_A005125
194 #define CONFIG_SYS_FSL_ERRATUM_A004477
195 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
197 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
198 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
199 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
200 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
201 #define CONFIG_SYS_NUM_FMAN 1
202 #define CONFIG_SYS_NUM_FM1_DTSEC 5
203 #define CONFIG_SYS_NUM_FM1_10GEC 1
204 #define CONFIG_NUM_DDR_CONTROLLERS 1
205 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
206 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
207 #define CONFIG_SYS_FSL_TBCLK_DIV 32
208 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
209 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
210 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
211 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
213 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
214 #define CONFIG_SYS_FSL_ERRATUM_USB14
215 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
216 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
217 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
218 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
219 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
220 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
221 #define CONFIG_SYS_FSL_ERRATUM_A004510
222 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
223 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
224 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
225 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
226 #define CONFIG_SYS_FSL_ERRATUM_A004849
227 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
228 #define CONFIG_SYS_FSL_ERRATUM_A006261
229 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
231 #elif defined(CONFIG_ARCH_P3041)
232 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
233 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
234 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
235 #define CONFIG_SYS_NUM_FMAN 1
236 #define CONFIG_SYS_NUM_FM1_DTSEC 5
237 #define CONFIG_SYS_NUM_FM1_10GEC 1
238 #define CONFIG_NUM_DDR_CONTROLLERS 1
239 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
240 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
241 #define CONFIG_SYS_FSL_TBCLK_DIV 32
242 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
243 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
244 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
245 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
246 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
248 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
249 #define CONFIG_SYS_FSL_ERRATUM_USB14
250 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
251 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
252 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
253 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
254 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
255 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
256 #define CONFIG_SYS_FSL_ERRATUM_A004510
257 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
258 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
259 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
260 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
261 #define CONFIG_SYS_FSL_ERRATUM_A004849
262 #define CONFIG_SYS_FSL_ERRATUM_A005812
263 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
264 #define CONFIG_SYS_FSL_ERRATUM_A006261
265 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
267 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
268 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
269 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
270 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
271 #define CONFIG_SYS_NUM_FMAN 2
272 #define CONFIG_SYS_NUM_FM1_DTSEC 4
273 #define CONFIG_SYS_NUM_FM2_DTSEC 4
274 #define CONFIG_SYS_NUM_FM1_10GEC 1
275 #define CONFIG_SYS_NUM_FM2_10GEC 1
276 #define CONFIG_NUM_DDR_CONTROLLERS 2
277 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
278 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
279 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
280 #define CONFIG_SYS_FSL_TBCLK_DIV 16
281 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
282 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
283 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
284 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
285 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
286 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
287 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
289 #define CONFIG_SYS_P4080_ERRATUM_CPU22
290 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
291 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
292 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
293 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
294 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
295 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
296 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
297 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
298 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
299 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
300 #define CONFIG_SYS_FSL_RMU
301 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
302 #define CONFIG_SYS_FSL_ERRATUM_A004510
303 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
304 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
305 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
306 #define CONFIG_SYS_FSL_ERRATUM_A004849
307 #define CONFIG_SYS_FSL_ERRATUM_A004580
308 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
309 #define CONFIG_SYS_FSL_ERRATUM_A005812
310 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
311 #define CONFIG_SYS_FSL_ERRATUM_A007075
312 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
314 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
315 #define CONFIG_SYS_PPC64 /* 64-bit core */
316 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
317 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
318 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
319 #define CONFIG_SYS_NUM_FMAN 1
320 #define CONFIG_SYS_NUM_FM1_DTSEC 5
321 #define CONFIG_SYS_NUM_FM1_10GEC 1
322 #define CONFIG_NUM_DDR_CONTROLLERS 2
323 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
324 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
325 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
326 #define CONFIG_SYS_FSL_TBCLK_DIV 32
327 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
328 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
329 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
330 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
331 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
332 #define CONFIG_SYS_FSL_ERRATUM_USB14
333 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
334 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
335 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
336 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
337 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
338 #define CONFIG_SYS_FSL_ERRATUM_A004510
339 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
340 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
341 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
342 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
343 #define CONFIG_SYS_FSL_ERRATUM_A006261
344 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
346 #elif defined(CONFIG_ARCH_P5040)
347 #define CONFIG_SYS_PPC64
348 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
349 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
350 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
351 #define CONFIG_SYS_NUM_FMAN 2
352 #define CONFIG_SYS_NUM_FM1_DTSEC 5
353 #define CONFIG_SYS_NUM_FM1_10GEC 1
354 #define CONFIG_SYS_NUM_FM2_DTSEC 5
355 #define CONFIG_SYS_NUM_FM2_10GEC 1
356 #define CONFIG_NUM_DDR_CONTROLLERS 2
357 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
358 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
359 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
360 #define CONFIG_SYS_FSL_TBCLK_DIV 16
361 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
362 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
363 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
364 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
365 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
366 #define CONFIG_SYS_FSL_ERRATUM_USB14
367 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
368 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
369 #define CONFIG_SYS_FSL_ERRATUM_A004699
370 #define CONFIG_SYS_FSL_ERRATUM_A004510
371 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
372 #define CONFIG_SYS_FSL_ERRATUM_A006261
373 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
374 #define CONFIG_SYS_FSL_ERRATUM_A005812
376 #elif defined(CONFIG_ARCH_BSC9131)
377 #define CONFIG_FSL_SDHC_V2_3
378 #define CONFIG_TSECV2
379 #define CONFIG_NUM_DDR_CONTROLLERS 1
380 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
381 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
382 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
383 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
384 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
385 #define CONFIG_NAND_FSL_IFC
386 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
387 #define CONFIG_SYS_FSL_ERRATUM_A005125
388 #define CONFIG_SYS_FSL_ERRATUM_A004477
389 #define CONFIG_ESDHC_HC_BLK_ADDR
391 #elif defined(CONFIG_ARCH_BSC9132)
392 #define CONFIG_FSL_SDHC_V2_3
393 #define CONFIG_TSECV2
394 #define CONFIG_NUM_DDR_CONTROLLERS 2
395 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
396 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
397 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
398 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
399 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
400 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
401 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
402 #define CONFIG_NAND_FSL_IFC
403 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
404 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
405 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
406 #define CONFIG_SYS_FSL_ERRATUM_A005125
407 #define CONFIG_SYS_FSL_ERRATUM_A005434
408 #define CONFIG_SYS_FSL_ERRATUM_A004477
409 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
410 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
411 #define CONFIG_ESDHC_HC_BLK_ADDR
413 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
415 #define CONFIG_SYS_PPC64 /* 64-bit core */
416 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
417 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
418 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
419 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
420 #ifdef CONFIG_ARCH_T4240
421 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
422 #define CONFIG_SYS_NUM_FM1_DTSEC 8
423 #define CONFIG_SYS_NUM_FM1_10GEC 2
424 #define CONFIG_SYS_NUM_FM2_DTSEC 8
425 #define CONFIG_SYS_NUM_FM2_10GEC 2
426 #define CONFIG_NUM_DDR_CONTROLLERS 3
427 #define CONFIG_SYS_FSL_ERRATUM_A006261
429 #define CONFIG_SYS_NUM_FM1_DTSEC 6
430 #define CONFIG_SYS_NUM_FM1_10GEC 1
431 #define CONFIG_SYS_NUM_FM2_DTSEC 8
432 #define CONFIG_SYS_NUM_FM2_10GEC 1
433 #define CONFIG_NUM_DDR_CONTROLLERS 2
434 #if defined(CONFIG_ARCH_T4160)
435 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
438 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
439 #define CONFIG_SYS_FSL_SRDS_1
440 #define CONFIG_SYS_FSL_SRDS_2
441 #define CONFIG_SYS_FSL_SRDS_3
442 #define CONFIG_SYS_FSL_SRDS_4
443 #define CONFIG_SYS_NUM_FMAN 2
444 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
445 #define CONFIG_SYS_PME_CLK 0
446 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
447 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
448 #define CONFIG_SYS_FMAN_V3
449 #define CONFIG_SYS_FM1_CLK 3
450 #define CONFIG_SYS_FM2_CLK 3
451 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
452 #define CONFIG_SYS_FSL_TBCLK_DIV 16
453 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
454 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
455 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
456 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
457 #define CONFIG_SYS_FSL_SRIO_LIODN
458 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
459 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
460 #define CONFIG_SYS_FSL_ERRATUM_A004468
461 #define CONFIG_SYS_FSL_ERRATUM_A005871
462 #define CONFIG_SYS_FSL_ERRATUM_A006379
463 #define CONFIG_SYS_FSL_ERRATUM_A007186
464 #define CONFIG_SYS_FSL_ERRATUM_A006593
465 #define CONFIG_SYS_FSL_ERRATUM_A007798
466 #define CONFIG_SYS_FSL_ERRATUM_A009942
467 #define CONFIG_SYS_FSL_SFP_VER_3_0
468 #define CONFIG_SYS_FSL_PCI_VER_3_X
470 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
472 #define CONFIG_SYS_PPC64 /* 64-bit core */
473 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
474 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
475 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
476 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
477 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
478 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
479 #define CONFIG_SYS_FSL_SRDS_1
480 #define CONFIG_SYS_FSL_SRDS_2
481 #define CONFIG_SYS_MAPLE
482 #define CONFIG_SYS_CPRI
483 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
484 #define CONFIG_SYS_NUM_FMAN 1
485 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
486 #define CONFIG_SYS_FM1_CLK 0
487 #define CONFIG_SYS_CPRI_CLK 3
488 #define CONFIG_SYS_ULB_CLK 4
489 #define CONFIG_SYS_ETVPE_CLK 1
490 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
491 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
492 #define CONFIG_SYS_FMAN_V3
493 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
494 #define CONFIG_SYS_FSL_TBCLK_DIV 16
495 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
496 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
497 #define CONFIG_SYS_FSL_ERRATUM_A005871
498 #define CONFIG_SYS_FSL_ERRATUM_A006379
499 #define CONFIG_SYS_FSL_ERRATUM_A007186
500 #define CONFIG_SYS_FSL_ERRATUM_A006593
501 #define CONFIG_SYS_FSL_ERRATUM_A007075
502 #define CONFIG_SYS_FSL_ERRATUM_A006475
503 #define CONFIG_SYS_FSL_ERRATUM_A006384
504 #define CONFIG_SYS_FSL_ERRATUM_A007212
505 #define CONFIG_SYS_FSL_ERRATUM_A004477
506 #define CONFIG_SYS_FSL_ERRATUM_A009942
507 #define CONFIG_SYS_FSL_SFP_VER_3_0
509 #ifdef CONFIG_ARCH_B4860
510 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
511 #define CONFIG_MAX_DSP_CPUS 12
512 #define CONFIG_NUM_DSP_CPUS 6
513 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
514 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
515 #define CONFIG_SYS_NUM_FM1_DTSEC 6
516 #define CONFIG_SYS_NUM_FM1_10GEC 2
517 #define CONFIG_NUM_DDR_CONTROLLERS 2
518 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
519 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
520 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
521 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
522 #define CONFIG_SYS_FSL_SRIO_LIODN
524 #define CONFIG_MAX_DSP_CPUS 2
525 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
526 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
527 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
528 #define CONFIG_SYS_NUM_FM1_DTSEC 4
529 #define CONFIG_SYS_NUM_FM1_10GEC 0
530 #define CONFIG_NUM_DDR_CONTROLLERS 1
533 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
535 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
536 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
537 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
538 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
539 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
540 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
541 #define CONFIG_SYS_FSL_SRDS_1
542 #define CONFIG_SYS_NUM_FMAN 1
543 #define CONFIG_SYS_NUM_FM1_DTSEC 5
544 #define CONFIG_NUM_DDR_CONTROLLERS 1
545 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
546 #define CONFIG_PME_PLAT_CLK_DIV 2
547 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
548 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
549 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
550 #define CONFIG_SYS_FSL_ERRATUM_A008044
551 #define CONFIG_SYS_FMAN_V3
552 #define CONFIG_FM_PLAT_CLK_DIV 1
553 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
554 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
555 per rcw field value */
556 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
557 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
558 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
559 #define CONFIG_SYS_FSL_TBCLK_DIV 16
560 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
561 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
562 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
563 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
564 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
565 #define QE_MURAM_SIZE 0x6000UL
566 #define MAX_QE_RISC 1
567 #define QE_NUM_OF_SNUM 28
568 #define CONFIG_SYS_FSL_SFP_VER_3_0
569 #define CONFIG_SYS_FSL_ERRATUM_A008378
570 #define CONFIG_SYS_FSL_ERRATUM_A009663
571 #define CONFIG_SYS_FSL_ERRATUM_A009942
573 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
575 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
576 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
577 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
578 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
579 #define CONFIG_SYS_FMAN_V3
580 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
581 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
582 #define CONFIG_SYS_FSL_SRDS_1
583 #define CONFIG_SYS_NUM_FMAN 1
584 #define CONFIG_SYS_NUM_FM1_DTSEC 4
585 #define CONFIG_SYS_NUM_FM1_10GEC 1
586 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
587 #define CONFIG_NUM_DDR_CONTROLLERS 1
588 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
589 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
590 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
591 #define CONFIG_SYS_FM1_CLK 0
592 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
593 per rcw field value */
594 #define CONFIG_QBMAN_CLK_DIV 1
595 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
596 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
597 #define CONFIG_SYS_FSL_TBCLK_DIV 16
598 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
599 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
600 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
601 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
602 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
603 #define QE_MURAM_SIZE 0x6000UL
604 #define MAX_QE_RISC 1
605 #define QE_NUM_OF_SNUM 28
606 #define CONFIG_SYS_FSL_SFP_VER_3_0
607 #define CONFIG_SYS_FSL_ERRATUM_A008378
608 #define CONFIG_SYS_FSL_ERRATUM_A009663
609 #define CONFIG_SYS_FSL_ERRATUM_A009942
611 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
613 #define CONFIG_SYS_PPC64 /* 64-bit core */
614 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
615 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
616 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
617 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
618 #define CONFIG_SYS_FSL_QMAN_V3
619 #define CONFIG_SYS_NUM_FMAN 1
620 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
621 #define CONFIG_SYS_FSL_SRDS_1
622 #define CONFIG_SYS_FSL_PCI_VER_3_X
623 #if defined(CONFIG_ARCH_T2080)
624 #define CONFIG_SYS_NUM_FM1_DTSEC 8
625 #define CONFIG_SYS_NUM_FM1_10GEC 4
626 #define CONFIG_SYS_FSL_SRDS_2
627 #define CONFIG_SYS_FSL_SRIO_LIODN
628 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
629 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
630 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
631 #elif defined(CONFIG_ARCH_T2081)
632 #define CONFIG_SYS_NUM_FM1_DTSEC 6
633 #define CONFIG_SYS_NUM_FM1_10GEC 2
635 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
636 #define CONFIG_NUM_DDR_CONTROLLERS 1
637 #define CONFIG_PME_PLAT_CLK_DIV 1
638 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
639 #define CONFIG_SYS_FM1_CLK 0
640 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
641 per rcw field value */
642 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
643 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
644 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
645 #define CONFIG_SYS_FMAN_V3
646 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
647 #define CONFIG_SYS_FSL_TBCLK_DIV 16
648 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
649 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
650 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
651 #define CONFIG_SYS_FSL_ERRATUM_A007212
652 #define CONFIG_SYS_FSL_SFP_VER_3_0
653 #define CONFIG_SYS_FSL_ISBC_VER 2
654 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
655 #define CONFIG_SYS_FSL_ERRATUM_A006593
656 #define CONFIG_SYS_FSL_ERRATUM_A007186
657 #define CONFIG_SYS_FSL_ERRATUM_A006379
658 #define CONFIG_SYS_FSL_ERRATUM_A009942
659 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
660 #define CONFIG_SYS_FSL_SFP_VER_3_0
663 #elif defined(CONFIG_ARCH_C29X)
664 #define CONFIG_FSL_SDHC_V2_3
665 #define CONFIG_TSECV2_1
666 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
667 #define CONFIG_NUM_DDR_CONTROLLERS 1
668 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
669 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
670 #define CONFIG_SYS_FSL_ERRATUM_A005125
671 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
672 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
674 #elif defined(CONFIG_ARCH_QEMU_E500)
677 #error Processor type not defined for this platform
681 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
683 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
686 #if !defined(CONFIG_ARCH_C29X)
687 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
690 #endif /* _ASM_MPC85xx_CONFIG_H_ */