2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef DDR2_DIMM_PARAMS_H
10 #define DDR2_DIMM_PARAMS_H
12 #define EDC_DATA_PARITY 1
14 #define EDC_AC_PARITY 4
16 /* Parameters for a DDR2 dimm computed from the SPD */
17 typedef struct dimm_params_s {
19 /* DIMM organization parameters */
20 char mpart[19]; /* guaranteed null terminated */
23 unsigned long long rank_density;
24 unsigned long long capacity;
25 unsigned int data_width;
26 unsigned int primary_sdram_width;
27 unsigned int ec_sdram_width;
28 unsigned int registered_dimm;
30 /* SDRAM device parameters */
31 unsigned int n_row_addr;
32 unsigned int n_col_addr;
33 unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
34 unsigned int n_banks_per_sdram_device;
35 unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
36 unsigned int row_density;
38 /* used in computing base address of DIMMs */
39 unsigned long long base_address;
41 unsigned int mirrored_dimm; /* only for ddr3 */
43 /* DIMM timing parameters */
45 unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
46 unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
47 unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
48 unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
52 * The range for these are 1000-10000 so a short should be sufficient
54 unsigned int tCKmin_X_ps;
55 unsigned int tCKmin_X_minus_1_ps;
56 unsigned int tCKmin_X_minus_2_ps;
57 unsigned int tCKmax_ps;
59 /* SPD-defined CAS latencies */
60 unsigned int caslat_X;
61 unsigned int caslat_X_minus_1;
62 unsigned int caslat_X_minus_2;
64 unsigned int caslat_lowest_derated; /* Derated CAS latency */
66 /* basic timing parameters */
71 unsigned int tWR_ps; /* maximum = 63750 ps */
72 unsigned int tWTR_ps; /* maximum = 63750 ps */
73 unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
76 unsigned int tRRD_ps; /* maximum = 63750 ps */
77 unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
79 unsigned int refresh_rate_ps;
81 /* DDR3 doesn't need these as below */
82 unsigned int tIS_ps; /* byte 32, spd->ca_setup */
83 unsigned int tIH_ps; /* byte 33, spd->ca_hold */
84 unsigned int tDS_ps; /* byte 34, spd->data_setup */
85 unsigned int tDH_ps; /* byte 35, spd->data_hold */
86 unsigned int tRTP_ps; /* byte 38, spd->trtp */
87 unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
88 unsigned int tQHS_ps; /* byte 45, spd->tqhs */
91 unsigned char rcw[16]; /* Register Control Word 0-15 */
94 extern unsigned int ddr_compute_dimm_parameters(
95 const generic_spd_eeprom_t *spd,
97 unsigned int dimm_number);