2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
13 * Pick a basic DDR Technology.
17 #define SDRAM_TYPE_DDR1 2
18 #define SDRAM_TYPE_DDR2 3
19 #define SDRAM_TYPE_LPDDR1 6
20 #define SDRAM_TYPE_DDR3 7
22 #define DDR_BL4 4 /* burst length 4 */
23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25 #define DDR_BL8 8 /* burst length 8 */
27 #define DDR3_RTT_OFF 0
28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
34 #if defined(CONFIG_FSL_DDR1)
35 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
36 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
37 #ifndef CONFIG_FSL_SDRAM_TYPE
38 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
40 #elif defined(CONFIG_FSL_DDR2)
41 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
42 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
43 #ifndef CONFIG_FSL_SDRAM_TYPE
44 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
46 #elif defined(CONFIG_FSL_DDR3)
47 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
48 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
49 #ifndef CONFIG_FSL_SDRAM_TYPE
50 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
52 #endif /* #if defined(CONFIG_FSL_DDR1) */
54 #define FSL_DDR_ODT_NEVER 0x0
55 #define FSL_DDR_ODT_CS 0x1
56 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
57 #define FSL_DDR_ODT_OTHER_DIMM 0x3
58 #define FSL_DDR_ODT_ALL 0x4
59 #define FSL_DDR_ODT_SAME_DIMM 0x5
60 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
61 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
63 /* define bank(chip select) interleaving mode */
64 #define FSL_DDR_CS0_CS1 0x40
65 #define FSL_DDR_CS2_CS3 0x20
66 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
67 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
69 /* define memory controller interleaving mode */
70 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
71 #define FSL_DDR_PAGE_INTERLEAVING 0x1
72 #define FSL_DDR_BANK_INTERLEAVING 0x2
73 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
75 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
77 #define SDRAM_CFG_MEM_EN 0x80000000
78 #define SDRAM_CFG_SREN 0x40000000
79 #define SDRAM_CFG_ECC_EN 0x20000000
80 #define SDRAM_CFG_RD_EN 0x10000000
81 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
82 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
83 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
84 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
85 #define SDRAM_CFG_DYN_PWR 0x00200000
86 #define SDRAM_CFG_32_BE 0x00080000
87 #define SDRAM_CFG_16_BE 0x00100000
88 #define SDRAM_CFG_8_BE 0x00040000
89 #define SDRAM_CFG_NCAP 0x00020000
90 #define SDRAM_CFG_2T_EN 0x00008000
91 #define SDRAM_CFG_BI 0x00000001
93 #define SDRAM_CFG2_D_INIT 0x00000010
94 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
96 #define TIMING_CFG_2_CPO_MASK 0x0F800000
98 #if defined(CONFIG_P4080)
99 #define RD_TO_PRE_MASK 0xf
100 #define RD_TO_PRE_SHIFT 13
101 #define WR_DATA_DELAY_MASK 0xf
102 #define WR_DATA_DELAY_SHIFT 9
104 #define RD_TO_PRE_MASK 0x7
105 #define RD_TO_PRE_SHIFT 13
106 #define WR_DATA_DELAY_MASK 0x7
107 #define WR_DATA_DELAY_SHIFT 10
111 #define MD_CNTL_MD_EN 0x80000000
112 #define MD_CNTL_CS_SEL_CS0 0x00000000
113 #define MD_CNTL_CS_SEL_CS1 0x10000000
114 #define MD_CNTL_CS_SEL_CS2 0x20000000
115 #define MD_CNTL_CS_SEL_CS3 0x30000000
116 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
117 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
118 #define MD_CNTL_MD_SEL_MR 0x00000000
119 #define MD_CNTL_MD_SEL_EMR 0x01000000
120 #define MD_CNTL_MD_SEL_EMR2 0x02000000
121 #define MD_CNTL_MD_SEL_EMR3 0x03000000
122 #define MD_CNTL_SET_REF 0x00800000
123 #define MD_CNTL_SET_PRE 0x00400000
124 #define MD_CNTL_CKE_CNTL_LOW 0x00100000
125 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
126 #define MD_CNTL_WRCW 0x00080000
127 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
130 #define DDR_CDR1_DHC_EN 0x80000000
132 /* Record of register values computed */
133 typedef struct fsl_ddr_cfg_regs_s {
137 unsigned int config_2;
138 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
139 unsigned int timing_cfg_3;
140 unsigned int timing_cfg_0;
141 unsigned int timing_cfg_1;
142 unsigned int timing_cfg_2;
143 unsigned int ddr_sdram_cfg;
144 unsigned int ddr_sdram_cfg_2;
145 unsigned int ddr_sdram_mode;
146 unsigned int ddr_sdram_mode_2;
147 unsigned int ddr_sdram_mode_3;
148 unsigned int ddr_sdram_mode_4;
149 unsigned int ddr_sdram_mode_5;
150 unsigned int ddr_sdram_mode_6;
151 unsigned int ddr_sdram_mode_7;
152 unsigned int ddr_sdram_mode_8;
153 unsigned int ddr_sdram_md_cntl;
154 unsigned int ddr_sdram_interval;
155 unsigned int ddr_data_init;
156 unsigned int ddr_sdram_clk_cntl;
157 unsigned int ddr_init_addr;
158 unsigned int ddr_init_ext_addr;
159 unsigned int timing_cfg_4;
160 unsigned int timing_cfg_5;
161 unsigned int ddr_zq_cntl;
162 unsigned int ddr_wrlvl_cntl;
163 unsigned int ddr_sr_cntr;
164 unsigned int ddr_sdram_rcw_1;
165 unsigned int ddr_sdram_rcw_2;
166 unsigned int ddr_eor;
167 unsigned int ddr_cdr1;
168 unsigned int ddr_cdr2;
169 unsigned int err_disable;
170 unsigned int err_int_en;
171 unsigned int debug[32];
172 } fsl_ddr_cfg_regs_t;
174 typedef struct memctl_options_partial_s {
175 unsigned int all_DIMMs_ECC_capable;
176 unsigned int all_DIMMs_tCKmax_ps;
177 unsigned int all_DIMMs_burst_lengths_bitmask;
178 unsigned int all_DIMMs_registered;
179 unsigned int all_DIMMs_unbuffered;
180 /* unsigned int lowest_common_SPD_caslat; */
181 unsigned int all_DIMMs_minimum_tRCD_ps;
182 } memctl_options_partial_t;
184 #define DDR_DATA_BUS_WIDTH_64 0
185 #define DDR_DATA_BUS_WIDTH_32 1
186 #define DDR_DATA_BUS_WIDTH_16 2
188 * Generalized parameters for memory controller configuration,
189 * might be a little specific to the FSL memory controller
191 typedef struct memctl_options_s {
193 * Memory organization parameters
195 * if DIMM is present in the system
196 * where DIMMs are with respect to chip select
197 * where chip selects are with respect to memory boundaries
199 unsigned int registered_dimm_en; /* use registered DIMM support */
201 /* Options local to a Chip Select */
202 struct cs_local_opts_s {
203 unsigned int auto_precharge;
204 unsigned int odt_rd_cfg;
205 unsigned int odt_wr_cfg;
206 unsigned int odt_rtt_norm;
207 unsigned int odt_rtt_wr;
208 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
210 /* Special configurations for chip select */
211 unsigned int memctl_interleaving;
212 unsigned int memctl_interleaving_mode;
213 unsigned int ba_intlv_ctl;
214 unsigned int addr_hash;
216 /* Operational mode parameters */
217 unsigned int ECC_mode; /* Use ECC? */
218 /* Initialize ECC using memory controller? */
219 unsigned int ECC_init_using_memctl;
220 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
221 /* SREN - self-refresh during sleep */
222 unsigned int self_refresh_in_sleep;
223 unsigned int dynamic_power; /* DYN_PWR */
224 /* memory data width to use (16-bit, 32-bit, 64-bit) */
225 unsigned int data_bus_width;
226 unsigned int burst_length; /* BL4, OTF and BL8 */
227 /* On-The-Fly Burst Chop enable */
228 unsigned int OTF_burst_chop_en;
229 /* mirrior DIMMs for DDR3 */
230 unsigned int mirrored_dimm;
231 unsigned int quad_rank_present;
232 unsigned int ap_en; /* address parity enable for RDIMM */
234 /* Global Timing Parameters */
235 unsigned int cas_latency_override;
236 unsigned int cas_latency_override_value;
237 unsigned int use_derated_caslat;
238 unsigned int additive_latency_override;
239 unsigned int additive_latency_override_value;
241 unsigned int clk_adjust; /* */
242 unsigned int cpo_override;
243 unsigned int write_data_delay; /* DQS adjust */
245 unsigned int wrlvl_override;
246 unsigned int wrlvl_sample; /* Write leveling */
247 unsigned int wrlvl_start;
249 unsigned int half_strength_driver_enable;
250 unsigned int twoT_en;
251 unsigned int threeT_en;
252 unsigned int bstopre;
253 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
254 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
257 unsigned int rtt_override; /* rtt_override enable */
258 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
259 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
261 /* Automatic self refresh */
262 unsigned int auto_self_refresh_en;
267 unsigned int wrlvl_en;
268 /* RCW override for RDIMM */
269 unsigned int rcw_override;
272 /* control register 1 */
273 unsigned int ddr_cdr1;
275 unsigned int trwt_override;
276 unsigned int trwt; /* read-to-write turnaround */
279 extern phys_size_t fsl_ddr_sdram(void);
280 extern phys_size_t fsl_ddr_sdram_size(void);
281 extern int fsl_use_spd(void);
282 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
283 unsigned int ctrl_num);
286 * The 85xx boards have a common prototype for fixed_sdram so put the
289 #ifdef CONFIG_MPC85xx
290 extern phys_size_t fixed_sdram(void);
293 #if defined(CONFIG_DDR_ECC)
294 extern void ddr_enable_ecc(unsigned int dram_size);
298 typedef struct fixed_ddr_parm{
301 fsl_ddr_cfg_regs_t *ddr_settings;