2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __ASM_PPC_FSL_IFC_H
22 #define __ASM_PPC_FSL_IFC_H
29 * CSPR - Chip Select Property Register
31 #define CSPR_BA 0xFFFF0000
32 #define CSPR_BA_SHIFT 16
33 #define CSPR_PORT_SIZE 0x00000180
34 #define CSPR_PORT_SIZE_SHIFT 7
36 #define CSPR_PORT_SIZE_8 0x00000080
37 /* Port Size 16 bit */
38 #define CSPR_PORT_SIZE_16 0x00000100
39 /* Port Size 32 bit */
40 #define CSPR_PORT_SIZE_32 0x00000180
42 #define CSPR_WP 0x00000040
43 #define CSPR_WP_SHIFT 6
45 #define CSPR_MSEL 0x00000006
46 #define CSPR_MSEL_SHIFT 1
48 #define CSPR_MSEL_NOR 0x00000000
50 #define CSPR_MSEL_NAND 0x00000002
52 #define CSPR_MSEL_GPCM 0x00000004
54 #define CSPR_V 0x00000001
55 #define CSPR_V_SHIFT 0
57 /* Convert an address into the right format for the CSPR Registers */
58 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
61 * Address Mask Register
63 #define IFC_AMASK_MASK 0xFFFF0000
64 #define IFC_AMASK_SHIFT 16
65 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
66 (__ilog2(n) - IFC_AMASK_SHIFT))
69 * Chip Select Option Register IFC_NAND Machine
71 /* Enable ECC Encoder */
72 #define CSOR_NAND_ECC_ENC_EN 0x80000000
73 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
74 /* 4 bit correction per 520 Byte sector */
75 #define CSOR_NAND_ECC_MODE_4 0x00000000
76 /* 8 bit correction per 528 Byte sector */
77 #define CSOR_NAND_ECC_MODE_8 0x10000000
78 /* Enable ECC Decoder */
79 #define CSOR_NAND_ECC_DEC_EN 0x04000000
80 /* Row Address Length */
81 #define CSOR_NAND_RAL_MASK 0x01800000
82 #define CSOR_NAND_RAL_SHIFT 20
83 #define CSOR_NAND_RAL_1 0x00000000
84 #define CSOR_NAND_RAL_2 0x00800000
85 #define CSOR_NAND_RAL_3 0x01000000
86 #define CSOR_NAND_RAL_4 0x01800000
87 /* Page Size 512b, 2k, 4k */
88 #define CSOR_NAND_PGS_MASK 0x00180000
89 #define CSOR_NAND_PGS_SHIFT 16
90 #define CSOR_NAND_PGS_512 0x00000000
91 #define CSOR_NAND_PGS_2K 0x00080000
92 #define CSOR_NAND_PGS_4K 0x00100000
93 /* Spare region Size */
94 #define CSOR_NAND_SPRZ_MASK 0x0000E000
95 #define CSOR_NAND_SPRZ_SHIFT 13
96 #define CSOR_NAND_SPRZ_16 0x00000000
97 #define CSOR_NAND_SPRZ_64 0x00002000
98 #define CSOR_NAND_SPRZ_128 0x00004000
99 #define CSOR_NAND_SPRZ_210 0x00006000
100 #define CSOR_NAND_SPRZ_218 0x00008000
101 #define CSOR_NAND_SPRZ_224 0x0000A000
102 /* Pages Per Block */
103 #define CSOR_NAND_PB_MASK 0x00000700
104 #define CSOR_NAND_PB_SHIFT 8
105 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
106 /* Time for Read Enable High to Output High Impedance */
107 #define CSOR_NAND_TRHZ_MASK 0x0000001C
108 #define CSOR_NAND_TRHZ_SHIFT 2
109 #define CSOR_NAND_TRHZ_20 0x00000000
110 #define CSOR_NAND_TRHZ_40 0x00000004
111 #define CSOR_NAND_TRHZ_60 0x00000008
112 #define CSOR_NAND_TRHZ_80 0x0000000C
113 #define CSOR_NAND_TRHZ_100 0x00000010
114 /* Buffer control disable */
115 #define CSOR_NAND_BCTLD 0x00000001
118 * Chip Select Option Register - NOR Flash Mode
120 /* Enable Address shift Mode */
121 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
122 /* Page Read Enable from NOR device */
123 #define CSOR_NOR_PGRD_EN 0x10000000
124 /* AVD Toggle Enable during Burst Program */
125 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
126 /* Address Data Multiplexing Shift */
127 #define CSOR_NOR_ADM_MASK 0x0003E000
128 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
129 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
130 /* Type of the NOR device hooked */
131 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
132 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
133 /* Time for Read Enable High to Output High Impedance */
134 #define CSOR_NOR_TRHZ_MASK 0x0000001C
135 #define CSOR_NOR_TRHZ_SHIFT 2
136 #define CSOR_NOR_TRHZ_20 0x00000000
137 #define CSOR_NOR_TRHZ_40 0x00000004
138 #define CSOR_NOR_TRHZ_60 0x00000008
139 #define CSOR_NOR_TRHZ_80 0x0000000C
140 #define CSOR_NOR_TRHZ_100 0x00000010
141 /* Buffer control disable */
142 #define CSOR_NOR_BCTLD 0x00000001
145 * Chip Select Option Register - GPCM Mode
147 /* GPCM Mode - Normal */
148 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
149 /* GPCM Mode - GenericASIC */
150 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
151 /* Parity Mode odd/even */
152 #define CSOR_GPCM_PARITY_EVEN 0x40000000
153 /* Parity Checking enable/disable */
154 #define CSOR_GPCM_PAR_EN 0x20000000
155 /* GPCM Timeout Count */
156 #define CSOR_GPCM_GPTO_MASK 0x0F000000
157 #define CSOR_GPCM_GPTO_SHIFT 24
158 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
159 /* GPCM External Access Termination mode for read access */
160 #define CSOR_GPCM_RGETA_EXT 0x00080000
161 /* GPCM External Access Termination mode for write access */
162 #define CSOR_GPCM_WGETA_EXT 0x00040000
163 /* Address Data Multiplexing Shift */
164 #define CSOR_GPCM_ADM_MASK 0x0003E000
165 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
166 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
167 /* Generic ASIC Parity error indication delay */
168 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
169 #define CSOR_GPCM_GAPERRD_SHIFT 7
170 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
171 /* Time for Read Enable High to Output High Impedance */
172 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
173 #define CSOR_GPCM_TRHZ_20 0x00000000
174 #define CSOR_GPCM_TRHZ_40 0x00000004
175 #define CSOR_GPCM_TRHZ_60 0x00000008
176 #define CSOR_GPCM_TRHZ_80 0x0000000C
177 #define CSOR_GPCM_TRHZ_100 0x00000010
178 /* Buffer control disable */
179 #define CSOR_GPCM_BCTLD 0x00000001
182 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
185 * FTIM0 - NAND Flash Mode
187 #define FTIM0_NAND 0x7EFF3F3F
188 #define FTIM0_NAND_TCCST_SHIFT 25
189 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
190 #define FTIM0_NAND_TWP_SHIFT 16
191 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
192 #define FTIM0_NAND_TWCHT_SHIFT 8
193 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
194 #define FTIM0_NAND_TWH_SHIFT 0
195 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
197 * FTIM1 - NAND Flash Mode
199 #define FTIM1_NAND 0xFFFF3FFF
200 #define FTIM1_NAND_TADLE_SHIFT 24
201 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
202 #define FTIM1_NAND_TWBE_SHIFT 16
203 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
204 #define FTIM1_NAND_TRR_SHIFT 8
205 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
206 #define FTIM1_NAND_TRP_SHIFT 0
207 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
209 * FTIM2 - NAND Flash Mode
211 #define FTIM2_NAND 0x1FE1F8FF
212 #define FTIM2_NAND_TRAD_SHIFT 21
213 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
214 #define FTIM2_NAND_TREH_SHIFT 11
215 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
216 #define FTIM2_NAND_TWHRE_SHIFT 0
217 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
219 * FTIM3 - NAND Flash Mode
221 #define FTIM3_NAND 0xFF000000
222 #define FTIM3_NAND_TWW_SHIFT 24
223 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
226 * FTIM0 - NOR Flash Mode
228 #define FTIM0_NOR 0xF03F3F3F
229 #define FTIM0_NOR_TACSE_SHIFT 28
230 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
231 #define FTIM0_NOR_TEADC_SHIFT 16
232 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
233 #define FTIM0_NOR_TAVDS_SHIFT 8
234 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
235 #define FTIM0_NOR_TEAHC_SHIFT 0
236 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
238 * FTIM1 - NOR Flash Mode
240 #define FTIM1_NOR 0xFF003F3F
241 #define FTIM1_NOR_TACO_SHIFT 24
242 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
243 #define FTIM1_NOR_TRAD_NOR_SHIFT 8
244 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
245 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
246 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
248 * FTIM2 - NOR Flash Mode
250 #define FTIM2_NOR 0x0F3CFCFF
251 #define FTIM2_NOR_TCS_SHIFT 24
252 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
253 #define FTIM2_NOR_TCH_SHIFT 18
254 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
255 #define FTIM2_NOR_TWPH_SHIFT 10
256 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
257 #define FTIM2_NOR_TWP_SHIFT 0
258 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
261 * FTIM0 - Normal GPCM Mode
263 #define FTIM0_GPCM 0xF03F3F3F
264 #define FTIM0_GPCM_TACSE_SHIFT 28
265 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
266 #define FTIM0_GPCM_TEADC_SHIFT 16
267 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
268 #define FTIM0_GPCM_TAVDS_SHIFT 8
269 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
270 #define FTIM0_GPCM_TEAHC_SHIFT 0
271 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
273 * FTIM1 - Normal GPCM Mode
275 #define FTIM1_GPCM 0xFF003F00
276 #define FTIM1_GPCM_TACO_SHIFT 24
277 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
278 #define FTIM1_GPCM_TRAD_SHIFT 8
279 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
281 * FTIM2 - Normal GPCM Mode
283 #define FTIM2_GPCM 0x0F3C00FF
284 #define FTIM2_GPCM_TCS_SHIFT 24
285 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
286 #define FTIM2_GPCM_TCH_SHIFT 18
287 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
288 #define FTIM2_GPCM_TWP_SHIFT 0
289 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
292 * Ready Busy Status Register (RB_STAT)
295 #define IFC_RB_STAT_READY_CS0 0x80000000
296 #define IFC_RB_STAT_READY_CS1 0x40000000
297 #define IFC_RB_STAT_READY_CS2 0x20000000
298 #define IFC_RB_STAT_READY_CS3 0x10000000
301 * General Control Register (GCR)
303 #define IFC_GCR_MASK 0x8000F800
304 /* reset all IFC hardware */
305 #define IFC_GCR_SOFT_RST_ALL 0x80000000
306 /* Turnaroud Time of external buffer */
307 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
308 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
311 * Common Event and Error Status Register (CM_EVTER_STAT)
313 /* Chip select error */
314 #define IFC_CM_EVTER_STAT_CSER 0x80000000
317 * Common Event and Error Enable Register (CM_EVTER_EN)
319 /* Chip select error checking enable */
320 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
323 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
325 /* Chip select error interrupt enable */
326 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
329 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
331 /* transaction type of error Read/Write */
332 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
333 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
334 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
337 * Clock Control Register (CCR)
339 #define IFC_CCR_MASK 0x0F0F8800
340 /* Clock division ratio */
341 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
342 #define IFC_CCR_CLK_DIV_SHIFT 24
343 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
344 /* IFC Clock Delay */
345 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
346 #define IFC_CCR_CLK_DLY_SHIFT 16
347 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
348 /* Invert IFC clock before sending out */
349 #define IFC_CCR_INV_CLK_EN 0x00008000
350 /* Fedback IFC Clock */
351 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
354 * Clock Status Register (CSR)
357 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
360 * IFC_NAND Machine Specific Registers
363 * NAND Configuration Register (NCFGR)
366 #define IFC_NAND_NCFGR_BOOT 0x80000000
367 /* Addressing Mode-ROW0+n/COL0 */
368 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
369 /* Addressing Mode-ROW0+n/COL0+n */
370 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
371 /* Number of loop iterations of FIR sequences for multi page operations */
372 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
373 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
374 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
375 /* Number of wait cycles */
376 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
377 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
380 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
382 /* General purpose FCM flash command bytes CMD0-CMD7 */
383 #define IFC_NAND_FCR0_CMD0 0xFF000000
384 #define IFC_NAND_FCR0_CMD0_SHIFT 24
385 #define IFC_NAND_FCR0_CMD1 0x00FF0000
386 #define IFC_NAND_FCR0_CMD1_SHIFT 16
387 #define IFC_NAND_FCR0_CMD2 0x0000FF00
388 #define IFC_NAND_FCR0_CMD2_SHIFT 8
389 #define IFC_NAND_FCR0_CMD3 0x000000FF
390 #define IFC_NAND_FCR0_CMD3_SHIFT 0
391 #define IFC_NAND_FCR1_CMD4 0xFF000000
392 #define IFC_NAND_FCR1_CMD4_SHIFT 24
393 #define IFC_NAND_FCR1_CMD5 0x00FF0000
394 #define IFC_NAND_FCR1_CMD5_SHIFT 16
395 #define IFC_NAND_FCR1_CMD6 0x0000FF00
396 #define IFC_NAND_FCR1_CMD6_SHIFT 8
397 #define IFC_NAND_FCR1_CMD7 0x000000FF
398 #define IFC_NAND_FCR1_CMD7_SHIFT 0
401 * Flash ROW and COL Address Register (ROWn, COLn)
403 /* Main/spare region locator */
404 #define IFC_NAND_COL_MS 0x80000000
406 #define IFC_NAND_COL_CA_MASK 0x00000FFF
409 * NAND Flash Byte Count Register (NAND_BC)
411 /* Byte Count for read/Write */
412 #define IFC_NAND_BC 0x000001FF
415 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
417 /* NAND Machine specific opcodes OP0-OP14*/
418 #define IFC_NAND_FIR0_OP0 0xFC000000
419 #define IFC_NAND_FIR0_OP0_SHIFT 26
420 #define IFC_NAND_FIR0_OP1 0x03F00000
421 #define IFC_NAND_FIR0_OP1_SHIFT 20
422 #define IFC_NAND_FIR0_OP2 0x000FC000
423 #define IFC_NAND_FIR0_OP2_SHIFT 14
424 #define IFC_NAND_FIR0_OP3 0x00003F00
425 #define IFC_NAND_FIR0_OP3_SHIFT 8
426 #define IFC_NAND_FIR0_OP4 0x000000FC
427 #define IFC_NAND_FIR0_OP4_SHIFT 2
428 #define IFC_NAND_FIR1_OP5 0xFC000000
429 #define IFC_NAND_FIR1_OP5_SHIFT 26
430 #define IFC_NAND_FIR1_OP6 0x03F00000
431 #define IFC_NAND_FIR1_OP6_SHIFT 20
432 #define IFC_NAND_FIR1_OP7 0x000FC000
433 #define IFC_NAND_FIR1_OP7_SHIFT 14
434 #define IFC_NAND_FIR1_OP8 0x00003F00
435 #define IFC_NAND_FIR1_OP8_SHIFT 8
436 #define IFC_NAND_FIR1_OP9 0x000000FC
437 #define IFC_NAND_FIR1_OP9_SHIFT 2
438 #define IFC_NAND_FIR2_OP10 0xFC000000
439 #define IFC_NAND_FIR2_OP10_SHIFT 26
440 #define IFC_NAND_FIR2_OP11 0x03F00000
441 #define IFC_NAND_FIR2_OP11_SHIFT 20
442 #define IFC_NAND_FIR2_OP12 0x000FC000
443 #define IFC_NAND_FIR2_OP12_SHIFT 14
444 #define IFC_NAND_FIR2_OP13 0x00003F00
445 #define IFC_NAND_FIR2_OP13_SHIFT 8
446 #define IFC_NAND_FIR2_OP14 0x000000FC
447 #define IFC_NAND_FIR2_OP14_SHIFT 2
450 * Instruction opcodes to be programmed
451 * in FIR registers- 6bits
453 enum ifc_nand_fir_opcodes {
491 * NAND Chip Select Register (NAND_CSEL)
493 #define IFC_NAND_CSEL 0x0C000000
494 #define IFC_NAND_CSEL_SHIFT 26
495 #define IFC_NAND_CSEL_CS0 0x00000000
496 #define IFC_NAND_CSEL_CS1 0x04000000
497 #define IFC_NAND_CSEL_CS2 0x08000000
498 #define IFC_NAND_CSEL_CS3 0x0C000000
501 * NAND Operation Sequence Start (NANDSEQ_STRT)
503 /* NAND Flash Operation Start */
504 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
505 /* Automatic Erase */
506 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
507 /* Automatic Program */
508 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
509 /* Automatic Copyback */
510 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
511 /* Automatic Read Operation */
512 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
513 /* Automatic Status Read */
514 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
517 * NAND Event and Error Status Register (NAND_EVTER_STAT)
519 /* Operation Complete */
520 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
521 /* Flash Timeout Error */
522 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
523 /* Write Protect Error */
524 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
526 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
528 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
529 /* Boot Loadr Done */
530 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
531 /* Bad Block Indicator search select */
532 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
535 * NAND Flash Page Read Completion Event Status Register
536 * (PGRDCMPL_EVT_STAT)
538 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
539 /* Small Page 0-15 Done */
540 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
541 /* Large Page(2K) 0-3 Done */
542 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
543 /* Large Page(4K) 0-1 Done */
544 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
547 * NAND Event and Error Enable Register (NAND_EVTER_EN)
549 /* Operation complete event enable */
550 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
551 /* Page read complete event enable */
552 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
553 /* Flash Timeout error enable */
554 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
555 /* Write Protect error enable */
556 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
557 /* ECC error logging enable */
558 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
561 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
563 /* Enable interrupt for operation complete */
564 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
565 /* Enable interrupt for Page read complete */
566 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
567 /* Enable interrupt for Flash timeout error */
568 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
569 /* Enable interrupt for Write protect error */
570 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
571 /* Enable interrupt for ECC error*/
572 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
575 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
577 #define IFC_NAND_ERATTR0_MASK 0x0C080000
578 /* Error on CS0-3 for NAND */
579 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
580 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
581 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
582 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
583 /* Transaction type of error Read/Write */
584 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
587 * NAND Flash Status Register (NAND_FSR)
589 /* First byte of data read from read status op */
590 #define IFC_NAND_NFSR_RS0 0xFF000000
591 /* Second byte of data read from read status op */
592 #define IFC_NAND_NFSR_RS1 0x00FF0000
595 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
597 /* Number of ECC errors on sector n (n = 0-15) */
598 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
599 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
600 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
601 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
602 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
603 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
604 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
605 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
606 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
607 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
608 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
609 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
610 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
611 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
612 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
613 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
614 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
615 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
616 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
617 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
618 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
619 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
620 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
621 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
622 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
623 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
624 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
625 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
626 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
627 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
628 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
629 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
632 * NAND Control Register (NANDCR)
634 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
635 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
636 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
641 /* Trigger RCW load */
642 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
643 /* Trigget Auto Boot */
644 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
649 /* 1st read data byte when opcode SBRD */
650 #define IFC_NAND_MDR_RDATA0 0xFF000000
651 /* 2nd read data byte when opcode SBRD */
652 #define IFC_NAND_MDR_RDATA1 0x00FF0000
655 * NOR Machine Specific Registers
658 * NOR Event and Error Status Register (NOR_EVTER_STAT)
660 /* NOR Command Sequence Operation Complete */
661 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
662 /* Write Protect Error */
663 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
664 /* Command Sequence Timeout Error */
665 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
668 * NOR Event and Error Enable Register (NOR_EVTER_EN)
670 /* NOR Command Seq complete event enable */
671 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
672 /* Write Protect Error Checking Enable */
673 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
674 /* Timeout Error Enable */
675 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
678 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
680 /* Enable interrupt for OPC complete */
681 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
682 /* Enable interrupt for write protect error */
683 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
684 /* Enable interrupt for timeout error */
685 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
688 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
690 /* Source ID for error transaction */
691 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
692 /* AXI ID for error transation */
693 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
694 /* Chip select corresponds to NOR error */
695 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
696 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
697 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
698 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
699 /* Type of transaction read/write */
700 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
703 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
705 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
706 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
709 * NOR Control Register (NORCR)
711 #define IFC_NORCR_MASK 0x0F0F0000
712 /* No. of Address/Data Phase */
713 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
714 #define IFC_NORCR_NUM_PHASE_SHIFT 24
715 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
716 /* Sequence Timeout Count */
717 #define IFC_NORCR_STOCNT_MASK 0x000F0000
718 #define IFC_NORCR_STOCNT_SHIFT 16
719 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
722 * GPCM Machine specific registers
725 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
728 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
730 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
733 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
735 /* Timeout error enable */
736 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
737 /* Parity error enable */
738 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
741 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
743 /* Enable Interrupt for timeout error */
744 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
745 /* Enable Interrupt for Parity error */
746 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
749 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
751 /* Source ID for error transaction */
752 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
753 /* AXI ID for error transaction */
754 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
755 /* Chip select corresponds to GPCM error */
756 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
757 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
758 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
759 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
760 /* Type of transaction read/Write */
761 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
764 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
766 /* On which beat of address/data parity error is observed */
767 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
768 /* Parity Error on byte */
769 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
770 /* Parity Error reported in addr or data phase */
771 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
774 * GPCM Status Register (GPCM_STAT)
776 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
782 extern void print_ifc_regs(void);
783 extern void init_early_memctl_regs(void);
785 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
787 #define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
788 #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
789 #define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
790 #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
791 #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
792 #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
794 #define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
795 #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
796 #define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
797 #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
798 #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
799 #define set_ifc_ftim(i, j, v) \
800 (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
821 * IFC Controller NAND Machine registers
823 struct fsl_ifc_nand {
857 u32 pgrdcmpl_evt_stat;
861 u32 nand_evter_intr_en;
872 u32 nand_autoboot_trgr;
879 * IFC controller NOR Machine registers
886 u32 nor_evter_intr_en;
897 * IFC controller GPCM Machine registers
899 struct fsl_ifc_gpcm {
904 u32 gpcm_evter_intr_en;
913 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
914 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
915 #define IFC_CSPR_REG_LEN 148
916 #define IFC_AMASK_REG_LEN 144
917 #define IFC_CSOR_REG_LEN 144
918 #define IFC_FTIM_REG_LEN 576
920 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
921 CONFIG_SYS_FSL_IFC_BANK_COUNT
922 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
923 CONFIG_SYS_FSL_IFC_BANK_COUNT
924 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
925 CONFIG_SYS_FSL_IFC_BANK_COUNT
926 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
927 CONFIG_SYS_FSL_IFC_BANK_COUNT
929 #error IFC BANK count not vaild
932 #error IFC BANK count not defined
935 struct fsl_ifc_cspr {
941 struct fsl_ifc_amask {
946 struct fsl_ifc_csor {
952 struct fsl_ifc_ftim {
958 * IFC Controller Registers
963 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
964 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
965 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
966 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
967 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
968 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
969 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
970 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
979 u32 cm_evter_intr_en;
987 struct fsl_ifc_nand ifc_nand;
988 struct fsl_ifc_nor ifc_nor;
989 struct fsl_ifc_gpcm ifc_gpcm;
992 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
994 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
996 #endif /* CONFIG_FSL_IFC */
998 #endif /* __ASSEMBLY__ */
999 #endif /* __ASM_PPC_FSL_IFC_H */