2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __ASM_PPC_FSL_IFC_H
22 #define __ASM_PPC_FSL_IFC_H
28 * CSPR - Chip Select Property Register
30 #define CSPR_BA 0xFFFF0000
31 #define CSPR_BA_SHIFT 16
32 #define CSPR_PORT_SIZE 0x00000180
33 #define CSPR_PORT_SIZE_SHIFT 7
35 #define CSPR_PORT_SIZE_8 0x00000080
36 /* Port Size 16 bit */
37 #define CSPR_PORT_SIZE_16 0x00000100
38 /* Port Size 32 bit */
39 #define CSPR_PORT_SIZE_32 0x00000180
41 #define CSPR_WP 0x00000040
42 #define CSPR_WP_SHIFT 6
44 #define CSPR_MSEL 0x00000006
45 #define CSPR_MSEL_SHIFT 1
47 #define CSPR_MSEL_NOR 0x00000000
49 #define CSPR_MSEL_NAND 0x00000002
51 #define CSPR_MSEL_GPCM 0x00000004
53 #define CSPR_V 0x00000001
54 #define CSPR_V_SHIFT 0
56 /* Convert an address into the right format for the CSPR Registers */
57 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
60 * Address Mask Register
62 #define IFC_AMASK_MASK 0xFFFF0000
63 #define IFC_AMASK_SHIFT 16
64 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
65 (__ilog2(n) - IFC_AMASK_SHIFT))
68 * Chip Select Option Register IFC_NAND Machine
70 /* Enable ECC Encoder */
71 #define CSOR_NAND_ECC_ENC_EN 0x80000000
72 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
73 /* 4 bit correction per 520 Byte sector */
74 #define CSOR_NAND_ECC_MODE_4 0x00000000
75 /* 8 bit correction per 528 Byte sector */
76 #define CSOR_NAND_ECC_MODE_8 0x10000000
77 /* Enable ECC Decoder */
78 #define CSOR_NAND_ECC_DEC_EN 0x04000000
79 /* Row Address Length */
80 #define CSOR_NAND_RAL_MASK 0x01800000
81 #define CSOR_NAND_RAL_SHIFT 20
82 #define CSOR_NAND_RAL_1 0x00000000
83 #define CSOR_NAND_RAL_2 0x00800000
84 #define CSOR_NAND_RAL_3 0x01000000
85 #define CSOR_NAND_RAL_4 0x01800000
86 /* Page Size 512b, 2k, 4k */
87 #define CSOR_NAND_PGS_MASK 0x00180000
88 #define CSOR_NAND_PGS_SHIFT 16
89 #define CSOR_NAND_PGS_512 0x00000000
90 #define CSOR_NAND_PGS_2K 0x00080000
91 #define CSOR_NAND_PGS_4K 0x00100000
92 /* Spare region Size */
93 #define CSOR_NAND_SPRZ_MASK 0x0000E000
94 #define CSOR_NAND_SPRZ_SHIFT 13
95 #define CSOR_NAND_SPRZ_16 0x00000000
96 #define CSOR_NAND_SPRZ_64 0x00002000
97 #define CSOR_NAND_SPRZ_128 0x00004000
98 #define CSOR_NAND_SPRZ_210 0x00006000
99 #define CSOR_NAND_SPRZ_218 0x00008000
100 #define CSOR_NAND_SPRZ_224 0x0000A000
101 /* Pages Per Block */
102 #define CSOR_NAND_PB_MASK 0x00000700
103 #define CSOR_NAND_PB_SHIFT 8
104 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
105 /* Time for Read Enable High to Output High Impedance */
106 #define CSOR_NAND_TRHZ_MASK 0x0000001C
107 #define CSOR_NAND_TRHZ_SHIFT 2
108 #define CSOR_NAND_TRHZ_20 0x00000000
109 #define CSOR_NAND_TRHZ_40 0x00000004
110 #define CSOR_NAND_TRHZ_60 0x00000008
111 #define CSOR_NAND_TRHZ_80 0x0000000C
112 #define CSOR_NAND_TRHZ_100 0x00000010
113 /* Buffer control disable */
114 #define CSOR_NAND_BCTLD 0x00000001
117 * Chip Select Option Register - NOR Flash Mode
119 /* Enable Address shift Mode */
120 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
121 /* Page Read Enable from NOR device */
122 #define CSOR_NOR_PGRD_EN 0x10000000
123 /* AVD Toggle Enable during Burst Program */
124 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
125 /* Address Data Multiplexing Shift */
126 #define CSOR_NOR_ADM_MASK 0x0003E000
127 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
128 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
129 /* Type of the NOR device hooked */
130 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
131 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
132 /* Time for Read Enable High to Output High Impedance */
133 #define CSOR_NOR_TRHZ_MASK 0x0000001C
134 #define CSOR_NOR_TRHZ_SHIFT 2
135 #define CSOR_NOR_TRHZ_20 0x00000000
136 #define CSOR_NOR_TRHZ_40 0x00000004
137 #define CSOR_NOR_TRHZ_60 0x00000008
138 #define CSOR_NOR_TRHZ_80 0x0000000C
139 #define CSOR_NOR_TRHZ_100 0x00000010
140 /* Buffer control disable */
141 #define CSOR_NOR_BCTLD 0x00000001
144 * Chip Select Option Register - GPCM Mode
146 /* GPCM Mode - Normal */
147 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
148 /* GPCM Mode - GenericASIC */
149 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
150 /* Parity Mode odd/even */
151 #define CSOR_GPCM_PARITY_EVEN 0x40000000
152 /* Parity Checking enable/disable */
153 #define CSOR_GPCM_PAR_EN 0x20000000
154 /* GPCM Timeout Count */
155 #define CSOR_GPCM_GPTO_MASK 0x0F000000
156 #define CSOR_GPCM_GPTO_SHIFT 24
157 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
158 /* GPCM External Access Termination mode for read access */
159 #define CSOR_GPCM_RGETA_EXT 0x00080000
160 /* GPCM External Access Termination mode for write access */
161 #define CSOR_GPCM_WGETA_EXT 0x00040000
162 /* Address Data Multiplexing Shift */
163 #define CSOR_GPCM_ADM_MASK 0x0003E000
164 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
165 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
166 /* Generic ASIC Parity error indication delay */
167 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
168 #define CSOR_GPCM_GAPERRD_SHIFT 7
169 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
170 /* Time for Read Enable High to Output High Impedance */
171 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
172 #define CSOR_GPCM_TRHZ_20 0x00000000
173 #define CSOR_GPCM_TRHZ_40 0x00000004
174 #define CSOR_GPCM_TRHZ_60 0x00000008
175 #define CSOR_GPCM_TRHZ_80 0x0000000C
176 #define CSOR_GPCM_TRHZ_100 0x00000010
177 /* Buffer control disable */
178 #define CSOR_GPCM_BCTLD 0x00000001
181 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
184 * FTIM0 - NAND Flash Mode
186 #define FTIM0_NAND 0x7EFF3F3F
187 #define FTIM0_NAND_TCCST_SHIFT 25
188 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
189 #define FTIM0_NAND_TWP_SHIFT 16
190 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
191 #define FTIM0_NAND_TWCHT_SHIFT 8
192 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
193 #define FTIM0_NAND_TWH_SHIFT 0
194 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
196 * FTIM1 - NAND Flash Mode
198 #define FTIM1_NAND 0xFFFF3FFF
199 #define FTIM1_NAND_TADLE_SHIFT 24
200 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
201 #define FTIM1_NAND_TWBE_SHIFT 16
202 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
203 #define FTIM1_NAND_TRR_SHIFT 8
204 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
205 #define FTIM1_NAND_TRP_SHIFT 0
206 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
208 * FTIM2 - NAND Flash Mode
210 #define FTIM2_NAND 0x1FE1F8FF
211 #define FTIM2_NAND_TRAD_SHIFT 21
212 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
213 #define FTIM2_NAND_TREH_SHIFT 11
214 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
215 #define FTIM2_NAND_TWHRE_SHIFT 0
216 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
218 * FTIM3 - NAND Flash Mode
220 #define FTIM3_NAND 0xFF000000
221 #define FTIM3_NAND_TWW_SHIFT 24
222 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
225 * FTIM0 - NOR Flash Mode
227 #define FTIM0_NOR 0xF03F3F3F
228 #define FTIM0_NOR_TACSE_SHIFT 28
229 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
230 #define FTIM0_NOR_TEADC_SHIFT 16
231 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
232 #define FTIM0_NOR_TAVDS_SHIFT 8
233 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
234 #define FTIM0_NOR_TEAHC_SHIFT 0
235 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
237 * FTIM1 - NOR Flash Mode
239 #define FTIM1_NOR 0xFF003F3F
240 #define FTIM1_NOR_TACO_SHIFT 24
241 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
242 #define FTIM1_NOR_TRAD_NOR_SHIFT 8
243 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
244 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
245 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
247 * FTIM2 - NOR Flash Mode
249 #define FTIM2_NOR 0x0F3CFCFF
250 #define FTIM2_NOR_TCS_SHIFT 24
251 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
252 #define FTIM2_NOR_TCH_SHIFT 18
253 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
254 #define FTIM2_NOR_TWPH_SHIFT 10
255 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
256 #define FTIM2_NOR_TWP_SHIFT 0
257 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
260 * FTIM0 - Normal GPCM Mode
262 #define FTIM0_GPCM 0xF03F3F3F
263 #define FTIM0_GPCM_TACSE_SHIFT 28
264 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
265 #define FTIM0_GPCM_TEADC_SHIFT 16
266 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
267 #define FTIM0_GPCM_TAVDS_SHIFT 8
268 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
269 #define FTIM0_GPCM_TEAHC_SHIFT 0
270 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
272 * FTIM1 - Normal GPCM Mode
274 #define FTIM1_GPCM 0xFF003F00
275 #define FTIM1_GPCM_TACO_SHIFT 24
276 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
277 #define FTIM1_GPCM_TRAD_SHIFT 8
278 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
280 * FTIM2 - Normal GPCM Mode
282 #define FTIM2_GPCM 0x0F3C00FF
283 #define FTIM2_GPCM_TCS_SHIFT 24
284 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
285 #define FTIM2_GPCM_TCH_SHIFT 18
286 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
287 #define FTIM2_GPCM_TWP_SHIFT 0
288 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
291 * Ready Busy Status Register (RB_STAT)
294 #define IFC_RB_STAT_READY_CS0 0x80000000
295 #define IFC_RB_STAT_READY_CS1 0x40000000
296 #define IFC_RB_STAT_READY_CS2 0x20000000
297 #define IFC_RB_STAT_READY_CS3 0x10000000
300 * General Control Register (GCR)
302 #define IFC_GCR_MASK 0x8000F800
303 /* reset all IFC hardware */
304 #define IFC_GCR_SOFT_RST_ALL 0x80000000
305 /* Turnaroud Time of external buffer */
306 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
307 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
310 * Common Event and Error Status Register (CM_EVTER_STAT)
312 /* Chip select error */
313 #define IFC_CM_EVTER_STAT_CSER 0x80000000
316 * Common Event and Error Enable Register (CM_EVTER_EN)
318 /* Chip select error checking enable */
319 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
322 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
324 /* Chip select error interrupt enable */
325 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
328 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
330 /* transaction type of error Read/Write */
331 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
332 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
333 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
336 * Clock Control Register (CCR)
338 #define IFC_CCR_MASK 0x0F0F8800
339 /* Clock division ratio */
340 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
341 #define IFC_CCR_CLK_DIV_SHIFT 24
342 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
343 /* IFC Clock Delay */
344 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
345 #define IFC_CCR_CLK_DLY_SHIFT 16
346 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
347 /* Invert IFC clock before sending out */
348 #define IFC_CCR_INV_CLK_EN 0x00008000
349 /* Fedback IFC Clock */
350 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
353 * Clock Status Register (CSR)
356 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
359 * IFC_NAND Machine Specific Registers
362 * NAND Configuration Register (NCFGR)
365 #define IFC_NAND_NCFGR_BOOT 0x80000000
366 /* Addressing Mode-ROW0+n/COL0 */
367 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
368 /* Addressing Mode-ROW0+n/COL0+n */
369 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
370 /* Number of loop iterations of FIR sequences for multi page operations */
371 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
372 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
373 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
374 /* Number of wait cycles */
375 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
376 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
379 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
381 /* General purpose FCM flash command bytes CMD0-CMD7 */
382 #define IFC_NAND_FCR0_CMD0 0xFF000000
383 #define IFC_NAND_FCR0_CMD0_SHIFT 24
384 #define IFC_NAND_FCR0_CMD1 0x00FF0000
385 #define IFC_NAND_FCR0_CMD1_SHIFT 16
386 #define IFC_NAND_FCR0_CMD2 0x0000FF00
387 #define IFC_NAND_FCR0_CMD2_SHIFT 8
388 #define IFC_NAND_FCR0_CMD3 0x000000FF
389 #define IFC_NAND_FCR0_CMD3_SHIFT 0
390 #define IFC_NAND_FCR1_CMD4 0xFF000000
391 #define IFC_NAND_FCR1_CMD4_SHIFT 24
392 #define IFC_NAND_FCR1_CMD5 0x00FF0000
393 #define IFC_NAND_FCR1_CMD5_SHIFT 16
394 #define IFC_NAND_FCR1_CMD6 0x0000FF00
395 #define IFC_NAND_FCR1_CMD6_SHIFT 8
396 #define IFC_NAND_FCR1_CMD7 0x000000FF
397 #define IFC_NAND_FCR1_CMD7_SHIFT 0
400 * Flash ROW and COL Address Register (ROWn, COLn)
402 /* Main/spare region locator */
403 #define IFC_NAND_COL_MS 0x80000000
405 #define IFC_NAND_COL_CA_MASK 0x00000FFF
408 * NAND Flash Byte Count Register (NAND_BC)
410 /* Byte Count for read/Write */
411 #define IFC_NAND_BC 0x000001FF
414 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
416 /* NAND Machine specific opcodes OP0-OP14*/
417 #define IFC_NAND_FIR0_OP0 0xFC000000
418 #define IFC_NAND_FIR0_OP0_SHIFT 26
419 #define IFC_NAND_FIR0_OP1 0x03F00000
420 #define IFC_NAND_FIR0_OP1_SHIFT 20
421 #define IFC_NAND_FIR0_OP2 0x000FC000
422 #define IFC_NAND_FIR0_OP2_SHIFT 14
423 #define IFC_NAND_FIR0_OP3 0x00003F00
424 #define IFC_NAND_FIR0_OP3_SHIFT 8
425 #define IFC_NAND_FIR0_OP4 0x000000FC
426 #define IFC_NAND_FIR0_OP4_SHIFT 2
427 #define IFC_NAND_FIR1_OP5 0xFC000000
428 #define IFC_NAND_FIR1_OP5_SHIFT 26
429 #define IFC_NAND_FIR1_OP6 0x03F00000
430 #define IFC_NAND_FIR1_OP6_SHIFT 20
431 #define IFC_NAND_FIR1_OP7 0x000FC000
432 #define IFC_NAND_FIR1_OP7_SHIFT 14
433 #define IFC_NAND_FIR1_OP8 0x00003F00
434 #define IFC_NAND_FIR1_OP8_SHIFT 8
435 #define IFC_NAND_FIR1_OP9 0x000000FC
436 #define IFC_NAND_FIR1_OP9_SHIFT 2
437 #define IFC_NAND_FIR2_OP10 0xFC000000
438 #define IFC_NAND_FIR2_OP10_SHIFT 26
439 #define IFC_NAND_FIR2_OP11 0x03F00000
440 #define IFC_NAND_FIR2_OP11_SHIFT 20
441 #define IFC_NAND_FIR2_OP12 0x000FC000
442 #define IFC_NAND_FIR2_OP12_SHIFT 14
443 #define IFC_NAND_FIR2_OP13 0x00003F00
444 #define IFC_NAND_FIR2_OP13_SHIFT 8
445 #define IFC_NAND_FIR2_OP14 0x000000FC
446 #define IFC_NAND_FIR2_OP14_SHIFT 2
449 * Instruction opcodes to be programmed
450 * in FIR registers- 6bits
452 enum ifc_nand_fir_opcodes {
490 * NAND Chip Select Register (NAND_CSEL)
492 #define IFC_NAND_CSEL 0x0C000000
493 #define IFC_NAND_CSEL_SHIFT 26
494 #define IFC_NAND_CSEL_CS0 0x00000000
495 #define IFC_NAND_CSEL_CS1 0x04000000
496 #define IFC_NAND_CSEL_CS2 0x08000000
497 #define IFC_NAND_CSEL_CS3 0x0C000000
500 * NAND Operation Sequence Start (NANDSEQ_STRT)
502 /* NAND Flash Operation Start */
503 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
504 /* Automatic Erase */
505 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
506 /* Automatic Program */
507 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
508 /* Automatic Copyback */
509 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
510 /* Automatic Read Operation */
511 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
512 /* Automatic Status Read */
513 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
516 * NAND Event and Error Status Register (NAND_EVTER_STAT)
518 /* Operation Complete */
519 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
520 /* Flash Timeout Error */
521 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
522 /* Write Protect Error */
523 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
525 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
527 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
528 /* Boot Loadr Done */
529 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
530 /* Bad Block Indicator search select */
531 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
534 * NAND Flash Page Read Completion Event Status Register
535 * (PGRDCMPL_EVT_STAT)
537 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
538 /* Small Page 0-15 Done */
539 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
540 /* Large Page(2K) 0-3 Done */
541 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
542 /* Large Page(4K) 0-1 Done */
543 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
546 * NAND Event and Error Enable Register (NAND_EVTER_EN)
548 /* Operation complete event enable */
549 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
550 /* Page read complete event enable */
551 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
552 /* Flash Timeout error enable */
553 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
554 /* Write Protect error enable */
555 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
556 /* ECC error logging enable */
557 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
560 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
562 /* Enable interrupt for operation complete */
563 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
564 /* Enable interrupt for Page read complete */
565 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
566 /* Enable interrupt for Flash timeout error */
567 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
568 /* Enable interrupt for Write protect error */
569 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
570 /* Enable interrupt for ECC error*/
571 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
574 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
576 #define IFC_NAND_ERATTR0_MASK 0x0C080000
577 /* Error on CS0-3 for NAND */
578 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
579 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
580 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
581 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
582 /* Transaction type of error Read/Write */
583 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
586 * NAND Flash Status Register (NAND_FSR)
588 /* First byte of data read from read status op */
589 #define IFC_NAND_NFSR_RS0 0xFF000000
590 /* Second byte of data read from read status op */
591 #define IFC_NAND_NFSR_RS1 0x00FF0000
594 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
596 /* Number of ECC errors on sector n (n = 0-15) */
597 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
598 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
599 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
600 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
601 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
602 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
603 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
604 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
605 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
606 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
607 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
608 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
609 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
610 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
611 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
612 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
613 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
614 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
615 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
616 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
617 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
618 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
619 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
620 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
621 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
622 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
623 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
624 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
625 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
626 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
627 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
628 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
631 * NAND Control Register (NANDCR)
633 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
634 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
635 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
640 /* Trigger RCW load */
641 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
642 /* Trigget Auto Boot */
643 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
648 /* 1st read data byte when opcode SBRD */
649 #define IFC_NAND_MDR_RDATA0 0xFF000000
650 /* 2nd read data byte when opcode SBRD */
651 #define IFC_NAND_MDR_RDATA1 0x00FF0000
654 * NOR Machine Specific Registers
657 * NOR Event and Error Status Register (NOR_EVTER_STAT)
659 /* NOR Command Sequence Operation Complete */
660 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
661 /* Write Protect Error */
662 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
663 /* Command Sequence Timeout Error */
664 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
667 * NOR Event and Error Enable Register (NOR_EVTER_EN)
669 /* NOR Command Seq complete event enable */
670 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
671 /* Write Protect Error Checking Enable */
672 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
673 /* Timeout Error Enable */
674 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
677 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
679 /* Enable interrupt for OPC complete */
680 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
681 /* Enable interrupt for write protect error */
682 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
683 /* Enable interrupt for timeout error */
684 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
687 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
689 /* Source ID for error transaction */
690 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
691 /* AXI ID for error transation */
692 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
693 /* Chip select corresponds to NOR error */
694 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
695 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
696 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
697 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
698 /* Type of transaction read/write */
699 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
702 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
704 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
705 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
708 * NOR Control Register (NORCR)
710 #define IFC_NORCR_MASK 0x0F0F0000
711 /* No. of Address/Data Phase */
712 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
713 #define IFC_NORCR_NUM_PHASE_SHIFT 24
714 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
715 /* Sequence Timeout Count */
716 #define IFC_NORCR_STOCNT_MASK 0x000F0000
717 #define IFC_NORCR_STOCNT_SHIFT 16
718 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
721 * GPCM Machine specific registers
724 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
727 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
729 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
732 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
734 /* Timeout error enable */
735 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
736 /* Parity error enable */
737 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
740 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
742 /* Enable Interrupt for timeout error */
743 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
744 /* Enable Interrupt for Parity error */
745 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
748 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
750 /* Source ID for error transaction */
751 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
752 /* AXI ID for error transaction */
753 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
754 /* Chip select corresponds to GPCM error */
755 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
756 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
757 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
758 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
759 /* Type of transaction read/Write */
760 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
763 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
765 /* On which beat of address/data parity error is observed */
766 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
767 /* Parity Error on byte */
768 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
769 /* Parity Error reported in addr or data phase */
770 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
773 * GPCM Status Register (GPCM_STAT)
775 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
781 extern void print_ifc_regs(void);
782 extern void init_early_memctl_regs(void);
784 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
786 #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
787 #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
788 #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
789 #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
791 #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
792 #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
793 #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
794 #define set_ifc_ftim(i, j, v) \
795 (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
797 #define FSL_IFC_BANK_COUNT 4
814 * IFC Controller NAND Machine registers
816 struct fsl_ifc_nand {
850 u32 pgrdcmpl_evt_stat;
854 u32 nand_evter_intr_en;
865 u32 nand_autoboot_trgr;
872 * IFC controller NOR Machine registers
879 u32 nor_evter_intr_en;
890 * IFC controller GPCM Machine registers
892 struct fsl_ifc_gpcm {
897 u32 gpcm_evter_intr_en;
908 * IFC Controller Registers
916 } cspr_cs[FSL_IFC_BANK_COUNT];
921 } amask_cs[FSL_IFC_BANK_COUNT];
926 } csor_cs[FSL_IFC_BANK_COUNT];
931 } ftim_cs[FSL_IFC_BANK_COUNT];
941 u32 cm_evter_intr_en;
949 struct fsl_ifc_nand ifc_nand;
950 struct fsl_ifc_nor ifc_nor;
951 struct fsl_ifc_gpcm ifc_gpcm;
954 #endif /* __ASSEMBLY__ */
955 #endif /* __ASM_PPC_FSL_IFC_H */