2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __ASM_PPC_FSL_IFC_H
22 #define __ASM_PPC_FSL_IFC_H
28 * CSPR - Chip Select Property Register
30 #define CSPR_BA 0xFFFF0000
31 #define CSPR_BA_SHIFT 16
32 #define CSPR_PORT_SIZE 0x00000180
33 #define CSPR_PORT_SIZE_SHIFT 7
35 #define CSPR_PORT_SIZE_8 0x00000080
36 /* Port Size 16 bit */
37 #define CSPR_PORT_SIZE_16 0x00000100
38 /* Port Size 32 bit */
39 #define CSPR_PORT_SIZE_32 0x00000180
41 #define CSPR_WP 0x00000040
42 #define CSPR_WP_SHIFT 6
44 #define CSPR_MSEL 0x00000006
45 #define CSPR_MSEL_SHIFT 1
47 #define CSPR_MSEL_NOR 0x00000000
49 #define CSPR_MSEL_NAND 0x00000002
51 #define CSPR_MSEL_GPCM 0x00000004
53 #define CSPR_V 0x00000001
54 #define CSPR_V_SHIFT 0
56 /* Convert an address into the right format for the CSPR Registers */
57 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
60 * Address Mask Register
62 #define IFC_AMASK_MASK 0xFFFF0000
63 #define IFC_AMASK_SHIFT 16
64 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
65 (__ilog2(n) - IFC_AMASK_SHIFT))
68 * Chip Select Option Register IFC_NAND Machine
70 /* Enable ECC Encoder */
71 #define CSOR_NAND_ECC_ENC_EN 0x80000000
72 /* 4 bit correction per 520 Byte sector */
73 #define CSOR_NAND_ECC_MODE_4 0x00000000
74 /* 8 bit correction per 528 Byte sector */
75 #define CSOR_NAND_ECC_MODE_8 0x10000000
76 /* Enable ECC Decoder */
77 #define CSOR_NAND_ECC_DEC_EN 0x04000000
78 /* Row Address Length */
79 #define CSOR_NAND_RAL_MASK 0x01800000
80 #define CSOR_NAND_RAL_SHIFT 20
81 #define CSOR_NAND_RAL_1 0x00000000
82 #define CSOR_NAND_RAL_2 0x00800000
83 #define CSOR_NAND_RAL_3 0x01000000
84 #define CSOR_NAND_RAL_4 0x01800000
85 /* Page Size 512b, 2k, 4k */
86 #define CSOR_NAND_PGS_MASK 0x00180000
87 #define CSOR_NAND_PGS_SHIFT 16
88 #define CSOR_NAND_PGS_512 0x00000000
89 #define CSOR_NAND_PGS_2K 0x00080000
90 #define CSOR_NAND_PGS_4K 0x00100000
91 /* Spare region Size */
92 #define CSOR_NAND_SPRZ_MASK 0x0000E000
93 #define CSOR_NAND_SPRZ_SHIFT 13
94 #define CSOR_NAND_SPRZ_16 0x00000000
95 #define CSOR_NAND_SPRZ_64 0x00002000
96 #define CSOR_NAND_SPRZ_128 0x00004000
97 #define CSOR_NAND_SPRZ_210 0x00006000
98 #define CSOR_NAND_SPRZ_218 0x00008000
99 #define CSOR_NAND_SPRZ_224 0x0000A000
100 /* Pages Per Block */
101 #define CSOR_NAND_PB_MASK 0x00000700
102 #define CSOR_NAND_PB_SHIFT 8
103 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
104 /* Time for Read Enable High to Output High Impedance */
105 #define CSOR_NAND_TRHZ_MASK 0x0000001C
106 #define CSOR_NAND_TRHZ_SHIFT 2
107 #define CSOR_NAND_TRHZ_20 0x00000000
108 #define CSOR_NAND_TRHZ_40 0x00000004
109 #define CSOR_NAND_TRHZ_60 0x00000008
110 #define CSOR_NAND_TRHZ_80 0x0000000C
111 #define CSOR_NAND_TRHZ_100 0x00000010
112 /* Buffer control disable */
113 #define CSOR_NAND_BCTLD 0x00000001
116 * Chip Select Option Register - NOR Flash Mode
118 /* Enable Address shift Mode */
119 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
120 /* Page Read Enable from NOR device */
121 #define CSOR_NOR_PGRD_EN 0x10000000
122 /* AVD Toggle Enable during Burst Program */
123 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
124 /* Address Data Multiplexing Shift */
125 #define CSOR_NOR_ADM_MASK 0x0003E000
126 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
127 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
128 /* Type of the NOR device hooked */
129 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
130 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
131 /* Time for Read Enable High to Output High Impedance */
132 #define CSOR_NOR_TRHZ_MASK 0x0000001C
133 #define CSOR_NOR_TRHZ_SHIFT 2
134 #define CSOR_NOR_TRHZ_20 0x00000000
135 #define CSOR_NOR_TRHZ_40 0x00000004
136 #define CSOR_NOR_TRHZ_60 0x00000008
137 #define CSOR_NOR_TRHZ_80 0x0000000C
138 #define CSOR_NOR_TRHZ_100 0x00000010
139 /* Buffer control disable */
140 #define CSOR_NOR_BCTLD 0x00000001
143 * Chip Select Option Register - GPCM Mode
145 /* GPCM Mode - Normal */
146 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
147 /* GPCM Mode - GenericASIC */
148 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
149 /* Parity Mode odd/even */
150 #define CSOR_GPCM_PARITY_EVEN 0x40000000
151 /* Parity Checking enable/disable */
152 #define CSOR_GPCM_PAR_EN 0x20000000
153 /* GPCM Timeout Count */
154 #define CSOR_GPCM_GPTO_MASK 0x0F000000
155 #define CSOR_GPCM_GPTO_SHIFT 24
156 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
157 /* GPCM External Access Termination mode for read access */
158 #define CSOR_GPCM_RGETA_EXT 0x00080000
159 /* GPCM External Access Termination mode for write access */
160 #define CSOR_GPCM_WGETA_EXT 0x00040000
161 /* Address Data Multiplexing Shift */
162 #define CSOR_GPCM_ADM_MASK 0x0003E000
163 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
164 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
165 /* Generic ASIC Parity error indication delay */
166 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
167 #define CSOR_GPCM_GAPERRD_SHIFT 7
168 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
169 /* Time for Read Enable High to Output High Impedance */
170 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
171 #define CSOR_GPCM_TRHZ_20 0x00000000
172 #define CSOR_GPCM_TRHZ_40 0x00000004
173 #define CSOR_GPCM_TRHZ_60 0x00000008
174 #define CSOR_GPCM_TRHZ_80 0x0000000C
175 #define CSOR_GPCM_TRHZ_100 0x00000010
176 /* Buffer control disable */
177 #define CSOR_GPCM_BCTLD 0x00000001
180 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
183 * FTIM0 - NAND Flash Mode
185 #define FTIM0_NAND 0x7EFF3F3F
186 #define FTIM0_NAND_TCCST_SHIFT 25
187 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
188 #define FTIM0_NAND_TWP_SHIFT 16
189 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
190 #define FTIM0_NAND_TWCHT_SHIFT 8
191 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
192 #define FTIM0_NAND_TWH_SHIFT 0
193 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
195 * FTIM1 - NAND Flash Mode
197 #define FTIM1_NAND 0xFFFF3FFF
198 #define FTIM1_NAND_TADLE_SHIFT 24
199 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
200 #define FTIM1_NAND_TWBE_SHIFT 16
201 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
202 #define FTIM1_NAND_TRR_SHIFT 8
203 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
204 #define FTIM1_NAND_TRP_SHIFT 0
205 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
207 * FTIM2 - NAND Flash Mode
209 #define FTIM2_NAND 0x1FE1F8FF
210 #define FTIM2_NAND_TRAD_SHIFT 21
211 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
212 #define FTIM2_NAND_TREH_SHIFT 11
213 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
214 #define FTIM2_NAND_TWHRE_SHIFT 0
215 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
217 * FTIM3 - NAND Flash Mode
219 #define FTIM3_NAND 0xFF000000
220 #define FTIM3_NAND_TWW_SHIFT 24
221 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
224 * FTIM0 - NOR Flash Mode
226 #define FTIM0_NOR 0xF03F3F3F
227 #define FTIM0_NOR_TACSE_SHIFT 28
228 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
229 #define FTIM0_NOR_TEADC_SHIFT 16
230 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
231 #define FTIM0_NOR_TAVDS_SHIFT 8
232 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
233 #define FTIM0_NOR_TEAHC_SHIFT 0
234 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
236 * FTIM1 - NOR Flash Mode
238 #define FTIM1_NOR 0xFF003F3F
239 #define FTIM1_NOR_TACO_SHIFT 24
240 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
241 #define FTIM1_NOR_TRAD_NOR_SHIFT 8
242 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
243 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
244 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
246 * FTIM2 - NOR Flash Mode
248 #define FTIM2_NOR 0x0F3CFCFF
249 #define FTIM2_NOR_TCS_SHIFT 24
250 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
251 #define FTIM2_NOR_TCH_SHIFT 18
252 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
253 #define FTIM2_NOR_TWPH_SHIFT 10
254 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
255 #define FTIM2_NOR_TWP_SHIFT 0
256 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
259 * FTIM0 - Normal GPCM Mode
261 #define FTIM0_GPCM 0xF03F3F3F
262 #define FTIM0_GPCM_TACSE_SHIFT 28
263 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
264 #define FTIM0_GPCM_TEADC_SHIFT 16
265 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
266 #define FTIM0_GPCM_TAVDS_SHIFT 8
267 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
268 #define FTIM0_GPCM_TEAHC_SHIFT 0
269 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
271 * FTIM1 - Normal GPCM Mode
273 #define FTIM1_GPCM 0xFF003F00
274 #define FTIM1_GPCM_TACO_SHIFT 24
275 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
276 #define FTIM1_GPCM_TRAD_SHIFT 8
277 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
279 * FTIM2 - Normal GPCM Mode
281 #define FTIM2_GPCM 0x0F3C00FF
282 #define FTIM2_GPCM_TCS_SHIFT 24
283 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
284 #define FTIM2_GPCM_TCH_SHIFT 18
285 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
286 #define FTIM2_GPCM_TWP_SHIFT 0
287 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
290 * Ready Busy Status Register (RB_STAT)
293 #define IFC_RB_STAT_READY_CS0 0x80000000
294 #define IFC_RB_STAT_READY_CS1 0x40000000
295 #define IFC_RB_STAT_READY_CS2 0x20000000
296 #define IFC_RB_STAT_READY_CS3 0x10000000
299 * General Control Register (GCR)
301 #define IFC_GCR_MASK 0x8000F800
302 /* reset all IFC hardware */
303 #define IFC_GCR_SOFT_RST_ALL 0x80000000
304 /* Turnaroud Time of external buffer */
305 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
306 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
309 * Common Event and Error Status Register (CM_EVTER_STAT)
311 /* Chip select error */
312 #define IFC_CM_EVTER_STAT_CSER 0x80000000
315 * Common Event and Error Enable Register (CM_EVTER_EN)
317 /* Chip select error checking enable */
318 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
321 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
323 /* Chip select error interrupt enable */
324 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
327 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
329 /* transaction type of error Read/Write */
330 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
331 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
332 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
335 * Clock Control Register (CCR)
337 #define IFC_CCR_MASK 0x0F0F8800
338 /* Clock division ratio */
339 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
340 #define IFC_CCR_CLK_DIV_SHIFT 24
341 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
342 /* IFC Clock Delay */
343 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
344 #define IFC_CCR_CLK_DLY_SHIFT 16
345 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
346 /* Invert IFC clock before sending out */
347 #define IFC_CCR_INV_CLK_EN 0x00008000
348 /* Fedback IFC Clock */
349 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
352 * Clock Status Register (CSR)
355 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
358 * IFC_NAND Machine Specific Registers
361 * NAND Configuration Register (NCFGR)
364 #define IFC_NAND_NCFGR_BOOT 0x80000000
365 /* Addressing Mode-ROW0+n/COL0 */
366 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
367 /* Addressing Mode-ROW0+n/COL0+n */
368 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
369 /* Number of loop iterations of FIR sequences for multi page operations */
370 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
371 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
372 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
373 /* Number of wait cycles */
374 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
375 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
378 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
380 /* General purpose FCM flash command bytes CMD0-CMD7 */
381 #define IFC_NAND_FCR0_CMD0 0xFF000000
382 #define IFC_NAND_FCR0_CMD0_SHIFT 24
383 #define IFC_NAND_FCR0_CMD1 0x00FF0000
384 #define IFC_NAND_FCR0_CMD1_SHIFT 16
385 #define IFC_NAND_FCR0_CMD2 0x0000FF00
386 #define IFC_NAND_FCR0_CMD2_SHIFT 8
387 #define IFC_NAND_FCR0_CMD3 0x000000FF
388 #define IFC_NAND_FCR0_CMD3_SHIFT 0
389 #define IFC_NAND_FCR1_CMD4 0xFF000000
390 #define IFC_NAND_FCR1_CMD4_SHIFT 24
391 #define IFC_NAND_FCR1_CMD5 0x00FF0000
392 #define IFC_NAND_FCR1_CMD5_SHIFT 16
393 #define IFC_NAND_FCR1_CMD6 0x0000FF00
394 #define IFC_NAND_FCR1_CMD6_SHIFT 8
395 #define IFC_NAND_FCR1_CMD7 0x000000FF
396 #define IFC_NAND_FCR1_CMD7_SHIFT 0
399 * Flash ROW and COL Address Register (ROWn, COLn)
401 /* Main/spare region locator */
402 #define IFC_NAND_COL_MS 0x80000000
404 #define IFC_NAND_COL_CA_MASK 0x00000FFF
407 * NAND Flash Byte Count Register (NAND_BC)
409 /* Byte Count for read/Write */
410 #define IFC_NAND_BC 0x000001FF
413 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
415 /* NAND Machine specific opcodes OP0-OP14*/
416 #define IFC_NAND_FIR0_OP0 0xFC000000
417 #define IFC_NAND_FIR0_OP0_SHIFT 26
418 #define IFC_NAND_FIR0_OP1 0x03F00000
419 #define IFC_NAND_FIR0_OP1_SHIFT 20
420 #define IFC_NAND_FIR0_OP2 0x000FC000
421 #define IFC_NAND_FIR0_OP2_SHIFT 14
422 #define IFC_NAND_FIR0_OP3 0x00003F00
423 #define IFC_NAND_FIR0_OP3_SHIFT 8
424 #define IFC_NAND_FIR0_OP4 0x000000FC
425 #define IFC_NAND_FIR0_OP4_SHIFT 2
426 #define IFC_NAND_FIR1_OP5 0xFC000000
427 #define IFC_NAND_FIR1_OP5_SHIFT 26
428 #define IFC_NAND_FIR1_OP6 0x03F00000
429 #define IFC_NAND_FIR1_OP6_SHIFT 20
430 #define IFC_NAND_FIR1_OP7 0x000FC000
431 #define IFC_NAND_FIR1_OP7_SHIFT 14
432 #define IFC_NAND_FIR1_OP8 0x00003F00
433 #define IFC_NAND_FIR1_OP8_SHIFT 8
434 #define IFC_NAND_FIR1_OP9 0x000000FC
435 #define IFC_NAND_FIR1_OP9_SHIFT 2
436 #define IFC_NAND_FIR2_OP10 0xFC000000
437 #define IFC_NAND_FIR2_OP10_SHIFT 26
438 #define IFC_NAND_FIR2_OP11 0x03F00000
439 #define IFC_NAND_FIR2_OP11_SHIFT 20
440 #define IFC_NAND_FIR2_OP12 0x000FC000
441 #define IFC_NAND_FIR2_OP12_SHIFT 14
442 #define IFC_NAND_FIR2_OP13 0x00003F00
443 #define IFC_NAND_FIR2_OP13_SHIFT 8
444 #define IFC_NAND_FIR2_OP14 0x000000FC
445 #define IFC_NAND_FIR2_OP14_SHIFT 2
448 * Instruction opcodes to be programmed
449 * in FIR registers- 6bits
451 enum ifc_nand_fir_opcodes {
489 * NAND Chip Select Register (NAND_CSEL)
491 #define IFC_NAND_CSEL 0x0C000000
492 #define IFC_NAND_CSEL_SHIFT 26
493 #define IFC_NAND_CSEL_CS0 0x00000000
494 #define IFC_NAND_CSEL_CS1 0x04000000
495 #define IFC_NAND_CSEL_CS2 0x08000000
496 #define IFC_NAND_CSEL_CS3 0x0C000000
499 * NAND Operation Sequence Start (NANDSEQ_STRT)
501 /* NAND Flash Operation Start */
502 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
503 /* Automatic Erase */
504 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
505 /* Automatic Program */
506 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
507 /* Automatic Copyback */
508 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
509 /* Automatic Read Operation */
510 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
511 /* Automatic Status Read */
512 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
515 * NAND Event and Error Status Register (NAND_EVTER_STAT)
517 /* Operation Complete */
518 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
519 /* Flash Timeout Error */
520 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
521 /* Write Protect Error */
522 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
524 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
526 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
527 /* Boot Loadr Done */
528 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
529 /* Bad Block Indicator search select */
530 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
533 * NAND Flash Page Read Completion Event Status Register
534 * (PGRDCMPL_EVT_STAT)
536 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
537 /* Small Page 0-15 Done */
538 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
539 /* Large Page(2K) 0-3 Done */
540 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
541 /* Large Page(4K) 0-1 Done */
542 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
545 * NAND Event and Error Enable Register (NAND_EVTER_EN)
547 /* Operation complete event enable */
548 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
549 /* Page read complete event enable */
550 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
551 /* Flash Timeout error enable */
552 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
553 /* Write Protect error enable */
554 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
555 /* ECC error logging enable */
556 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
559 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
561 /* Enable interrupt for operation complete */
562 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
563 /* Enable interrupt for Page read complete */
564 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
565 /* Enable interrupt for Flash timeout error */
566 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
567 /* Enable interrupt for Write protect error */
568 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
569 /* Enable interrupt for ECC error*/
570 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
573 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
575 #define IFC_NAND_ERATTR0_MASK 0x0C080000
576 /* Error on CS0-3 for NAND */
577 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
578 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
579 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
580 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
581 /* Transaction type of error Read/Write */
582 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
585 * NAND Flash Status Register (NAND_FSR)
587 /* First byte of data read from read status op */
588 #define IFC_NAND_NFSR_RS0 0xFF000000
589 /* Second byte of data read from read status op */
590 #define IFC_NAND_NFSR_RS1 0x00FF0000
593 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
595 /* Number of ECC errors on sector n (n = 0-15) */
596 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
597 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
598 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
599 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
600 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
601 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
602 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
603 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
604 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
605 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
606 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
607 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
608 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
609 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
610 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
611 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
612 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
613 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
614 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
615 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
616 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
617 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
618 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
619 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
620 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
621 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
622 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
623 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
624 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
625 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
626 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
627 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
630 * NAND Control Register (NANDCR)
632 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
633 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
634 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
639 /* Trigger RCW load */
640 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
641 /* Trigget Auto Boot */
642 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
647 /* 1st read data byte when opcode SBRD */
648 #define IFC_NAND_MDR_RDATA0 0xFF000000
649 /* 2nd read data byte when opcode SBRD */
650 #define IFC_NAND_MDR_RDATA1 0x00FF0000
653 * NOR Machine Specific Registers
656 * NOR Event and Error Status Register (NOR_EVTER_STAT)
658 /* NOR Command Sequence Operation Complete */
659 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
660 /* Write Protect Error */
661 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
662 /* Command Sequence Timeout Error */
663 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
666 * NOR Event and Error Enable Register (NOR_EVTER_EN)
668 /* NOR Command Seq complete event enable */
669 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
670 /* Write Protect Error Checking Enable */
671 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
672 /* Timeout Error Enable */
673 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
676 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
678 /* Enable interrupt for OPC complete */
679 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
680 /* Enable interrupt for write protect error */
681 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
682 /* Enable interrupt for timeout error */
683 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
686 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
688 /* Source ID for error transaction */
689 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
690 /* AXI ID for error transation */
691 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
692 /* Chip select corresponds to NOR error */
693 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
694 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
695 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
696 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
697 /* Type of transaction read/write */
698 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
701 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
703 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
704 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
707 * NOR Control Register (NORCR)
709 #define IFC_NORCR_MASK 0x0F0F0000
710 /* No. of Address/Data Phase */
711 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
712 #define IFC_NORCR_NUM_PHASE_SHIFT 24
713 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
714 /* Sequence Timeout Count */
715 #define IFC_NORCR_STOCNT_MASK 0x000F0000
716 #define IFC_NORCR_STOCNT_SHIFT 16
717 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
720 * GPCM Machine specific registers
723 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
726 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
728 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
731 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
733 /* Timeout error enable */
734 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
735 /* Parity error enable */
736 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
739 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
741 /* Enable Interrupt for timeout error */
742 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
743 /* Enable Interrupt for Parity error */
744 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
747 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
749 /* Source ID for error transaction */
750 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
751 /* AXI ID for error transaction */
752 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
753 /* Chip select corresponds to GPCM error */
754 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
755 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
756 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
757 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
758 /* Type of transaction read/Write */
759 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
762 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
764 /* On which beat of address/data parity error is observed */
765 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
766 /* Parity Error on byte */
767 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
768 /* Parity Error reported in addr or data phase */
769 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
772 * GPCM Status Register (GPCM_STAT)
774 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
780 extern void print_ifc_regs(void);
781 extern void init_early_memctl_regs(void);
783 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
785 #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
786 #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
787 #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
788 #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
790 #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
791 #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
792 #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
793 #define set_ifc_ftim(i, j, v) \
794 (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
796 #define FSL_IFC_BANK_COUNT 4
813 * IFC Controller NAND Machine registers
815 struct fsl_ifc_nand {
849 u32 pgrdcmpl_evt_stat;
853 u32 nand_evter_intr_en;
867 u32 nand_autoboot_trgr;
874 * IFC controller NOR Machine registers
881 u32 nor_evter_intr_en;
892 * IFC controller GPCM Machine registers
894 struct fsl_ifc_gpcm {
899 u32 gpcm_evter_intr_en;
910 * IFC Controller Registers
918 } cspr_cs[FSL_IFC_BANK_COUNT];
923 } amask_cs[FSL_IFC_BANK_COUNT];
928 } csor_cs[FSL_IFC_BANK_COUNT];
933 } ftim_cs[FSL_IFC_BANK_COUNT];
943 u32 cm_evter_intr_en;
951 struct fsl_ifc_nand ifc_nand;
952 struct fsl_ifc_nor ifc_nor;
953 struct fsl_ifc_gpcm ifc_gpcm;
956 #endif /* __ASSEMBLY__ */
957 #endif /* __ASM_PPC_FSL_IFC_H */