2 * Copyright 2004-2011 Freescale Semiconductor, Inc.
4 * MPC83xx Internal Memory Map
7 * Dave Liu <daveliu@freescale.com>
8 * Tanya Jiang <tanya.jiang@freescale.com>
9 * Mandy Lavi <mandy.lavi@freescale.com>
10 * Eran Liberty <liberty@freescale.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
34 #include <asm/fsl_lbc.h>
35 #include <asm/fsl_dma.h>
40 typedef struct law83xx {
41 u32 bar; /* LBIU local access window base address register */
42 u32 ar; /* LBIU local access window attribute register */
46 * System configuration registers
48 typedef struct sysconf83xx {
49 u32 immrbar; /* Internal memory map base address register */
51 u32 altcbar; /* Alternate configuration base address register */
53 law83xx_t lblaw[4]; /* LBIU local access window */
55 law83xx_t pcilaw[2]; /* PCI local access window */
57 law83xx_t pcielaw[2]; /* PCI Express local access window */
59 law83xx_t ddrlaw[2]; /* DDR local access window */
61 u32 sgprl; /* System General Purpose Register Low */
62 u32 sgprh; /* System General Purpose Register High */
63 u32 spridr; /* System Part and Revision ID Register */
65 u32 spcr; /* System Priority Configuration Register */
66 u32 sicrl; /* System I/O Configuration Register Low */
67 u32 sicrh; /* System I/O Configuration Register High */
69 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
70 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
71 u32 ddrcdr; /* DDR Control Driver Register */
72 u32 ddrdsr; /* DDR Debug Status Register */
73 u32 obir; /* Output Buffer Impedance Register */
75 u32 pecr1; /* PCI Express control register 1 */
77 u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
79 u32 pecr2; /* PCI Express control register 2 */
85 * Watch Dog Timer (WDT) Registers
87 typedef struct wdt83xx {
89 u32 swcrr; /* System watchdog control register */
90 u32 swcnr; /* System watchdog count register */
92 u16 swsrr; /* System watchdog service register */
97 * RTC/PIT Module Registers
99 typedef struct rtclk83xx {
100 u32 cnr; /* control register */
101 u32 ldr; /* load register */
102 u32 psr; /* prescale register */
103 u32 ctr; /* counter value field register */
104 u32 evr; /* event register */
105 u32 alr; /* alarm register */
110 * Global timer module
112 typedef struct gtm83xx {
113 u8 cfr1; /* Timer1/2 Configuration */
115 u8 cfr2; /* Timer3/4 Configuration */
117 u16 mdr1; /* Timer1 Mode Register */
118 u16 mdr2; /* Timer2 Mode Register */
119 u16 rfr1; /* Timer1 Reference Register */
120 u16 rfr2; /* Timer2 Reference Register */
121 u16 cpr1; /* Timer1 Capture Register */
122 u16 cpr2; /* Timer2 Capture Register */
123 u16 cnr1; /* Timer1 Counter Register */
124 u16 cnr2; /* Timer2 Counter Register */
125 u16 mdr3; /* Timer3 Mode Register */
126 u16 mdr4; /* Timer4 Mode Register */
127 u16 rfr3; /* Timer3 Reference Register */
128 u16 rfr4; /* Timer4 Reference Register */
129 u16 cpr3; /* Timer3 Capture Register */
130 u16 cpr4; /* Timer4 Capture Register */
131 u16 cnr3; /* Timer3 Counter Register */
132 u16 cnr4; /* Timer4 Counter Register */
133 u16 evr1; /* Timer1 Event Register */
134 u16 evr2; /* Timer2 Event Register */
135 u16 evr3; /* Timer3 Event Register */
136 u16 evr4; /* Timer4 Event Register */
137 u16 psr1; /* Timer1 Prescaler Register */
138 u16 psr2; /* Timer2 Prescaler Register */
139 u16 psr3; /* Timer3 Prescaler Register */
140 u16 psr4; /* Timer4 Prescaler Register */
145 * Integrated Programmable Interrupt Controller
147 typedef struct ipic83xx {
148 u32 sicfr; /* System Global Interrupt Configuration Register */
149 u32 sivcr; /* System Global Interrupt Vector Register */
150 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
151 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
152 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
154 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
155 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
156 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
158 u32 sepnr; /* System External Interrupt Pending Register */
159 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
160 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
161 u32 semsr; /* System External Interrupt Mask Register */
162 u32 secnr; /* System External Interrupt Control Register */
163 u32 sersr; /* System Error Status Register */
164 u32 sermr; /* System Error Mask Register */
165 u32 sercr; /* System Error Control Register */
167 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
168 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
169 u32 sefcr; /* System External Interrupt Force Register */
170 u32 serfr; /* System Error Force Register */
171 u32 scvcr; /* System Critical Interrupt Vector Register */
172 u32 smvcr; /* System Management Interrupt Vector Register */
177 * System Arbiter Registers
179 typedef struct arbiter83xx {
180 u32 acr; /* Arbiter Configuration Register */
181 u32 atr; /* Arbiter Timers Register */
183 u32 aer; /* Arbiter Event Register */
184 u32 aidr; /* Arbiter Interrupt Definition Register */
185 u32 amr; /* Arbiter Mask Register */
186 u32 aeatr; /* Arbiter Event Attributes Register */
187 u32 aeadr; /* Arbiter Event Address Register */
188 u32 aerr; /* Arbiter Event Response Register */
195 typedef struct reset83xx {
196 u32 rcwl; /* Reset Configuration Word Low Register */
197 u32 rcwh; /* Reset Configuration Word High Register */
199 u32 rsr; /* Reset Status Register */
200 u32 rmr; /* Reset Mode Register */
201 u32 rpr; /* Reset protection Register */
202 u32 rcr; /* Reset Control Register */
203 u32 rcer; /* Reset Control Enable Register */
210 typedef struct clk83xx {
211 u32 spmr; /* system PLL mode Register */
212 u32 occr; /* output clock control Register */
213 u32 sccr; /* system clock control Register */
218 * Power Management Control Module
220 typedef struct pmc83xx {
221 u32 pmccr; /* PMC Configuration Register */
222 u32 pmcer; /* PMC Event Register */
223 u32 pmcmr; /* PMC Mask Register */
224 u32 pmccr1; /* PMC Configuration Register 1 */
225 u32 pmccr2; /* PMC Configuration Register 2 */
230 * General purpose I/O module
232 typedef struct gpio83xx {
233 u32 dir; /* direction register */
234 u32 odr; /* open drain register */
235 u32 dat; /* data register */
236 u32 ier; /* interrupt event register */
237 u32 imr; /* interrupt mask register */
238 u32 icr; /* external interrupt control register */
243 * QE Ports Interrupts Registers
245 typedef struct qepi83xx {
247 u32 qepier; /* QE Ports Interrupt Event Register */
248 u32 qepimr; /* QE Ports Interrupt Mask Register */
249 u32 qepicr; /* QE Ports Interrupt Control Register */
254 * QE Parallel I/O Ports
256 typedef struct gpio_n {
257 u32 podr; /* Open Drain Register */
258 u32 pdat; /* Data Register */
259 u32 dir1; /* direction register 1 */
260 u32 dir2; /* direction register 2 */
261 u32 ppar1; /* Pin Assignment Register 1 */
262 u32 ppar2; /* Pin Assignment Register 2 */
265 typedef struct qegpio83xx {
266 gpio_n_t ioport[0x7];
271 * QE Secondary Bus Access Windows
273 typedef struct qesba83xx {
274 u32 lbmcsar; /* Local bus memory controller start address */
275 u32 sdmcsar; /* Secondary DDR memory controller start address */
277 u32 lbmcear; /* Local bus memory controller end address */
278 u32 sdmcear; /* Secondary DDR memory controller end address */
280 u32 lbmcar; /* Local bus memory controller attributes */
281 u32 sdmcar; /* Secondary DDR memory controller attributes */
286 * DDR Memory Controller Memory Map
288 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
289 typedef struct ccsr_ddr {
290 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
292 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
294 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
296 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
298 u32 cs0_config; /* Chip Select Configuration */
299 u32 cs1_config; /* Chip Select Configuration */
300 u32 cs2_config; /* Chip Select Configuration */
301 u32 cs3_config; /* Chip Select Configuration */
303 u32 cs0_config_2; /* Chip Select Configuration 2 */
304 u32 cs1_config_2; /* Chip Select Configuration 2 */
305 u32 cs2_config_2; /* Chip Select Configuration 2 */
306 u32 cs3_config_2; /* Chip Select Configuration 2 */
308 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
309 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
310 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
311 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
312 u32 sdram_cfg; /* SDRAM Control Configuration */
313 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
314 u32 sdram_mode; /* SDRAM Mode Configuration */
315 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
316 u32 sdram_md_cntl; /* SDRAM Mode Control */
317 u32 sdram_interval; /* SDRAM Interval Configuration */
318 u32 sdram_data_init; /* SDRAM Data initialization */
320 u32 sdram_clk_cntl; /* SDRAM Clock Control */
322 u32 init_addr; /* training init addr */
323 u32 init_ext_addr; /* training init extended addr */
325 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
326 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
328 u32 ddr_zq_cntl; /* ZQ calibration control*/
329 u32 ddr_wrlvl_cntl; /* write leveling control*/
331 u32 ddr_sr_cntr; /* self refresh counter */
332 u32 ddr_sdram_rcw_1; /* Control Words 1 */
333 u32 ddr_sdram_rcw_2; /* Control Words 2 */
335 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
336 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
338 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
339 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
340 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
341 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
342 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
343 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
345 u32 ddr_dsr1; /* Debug Status 1 */
346 u32 ddr_dsr2; /* Debug Status 2 */
347 u32 ddr_cdr1; /* Control Driver 1 */
348 u32 ddr_cdr2; /* Control Driver 2 */
350 u32 ip_rev1; /* IP Block Revision 1 */
351 u32 ip_rev2; /* IP Block Revision 2 */
352 u32 eor; /* Enhanced Optimization Register */
354 u32 mtcr; /* Memory Test Control Register */
356 u32 mtp1; /* Memory Test Pattern 1 */
357 u32 mtp2; /* Memory Test Pattern 2 */
358 u32 mtp3; /* Memory Test Pattern 3 */
359 u32 mtp4; /* Memory Test Pattern 4 */
360 u32 mtp5; /* Memory Test Pattern 5 */
361 u32 mtp6; /* Memory Test Pattern 6 */
362 u32 mtp7; /* Memory Test Pattern 7 */
363 u32 mtp8; /* Memory Test Pattern 8 */
364 u32 mtp9; /* Memory Test Pattern 9 */
365 u32 mtp10; /* Memory Test Pattern 10 */
367 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
368 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
369 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
371 u32 capture_data_hi; /* Data Path Read Capture High */
372 u32 capture_data_lo; /* Data Path Read Capture Low */
373 u32 capture_ecc; /* Data Path Read Capture ECC */
375 u32 err_detect; /* Error Detect */
376 u32 err_disable; /* Error Disable */
378 u32 capture_attributes; /* Error Attrs Capture */
379 u32 capture_address; /* Error Addr Capture */
380 u32 capture_ext_address; /* Error Extended Addr Capture */
381 u32 err_sbe; /* Single-Bit ECC Error Management */
383 u32 debug[32]; /* debug_1 to debug_32 */
387 typedef struct ddr_cs_bnds {
392 typedef struct ddr83xx {
393 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
395 u32 cs_config[4]; /* Chip Select x Configuration */
397 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
398 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
399 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
400 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
401 u32 sdram_cfg; /* SDRAM Control Configuration */
402 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
403 u32 sdram_mode; /* SDRAM Mode Configuration */
404 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
405 u32 sdram_md_cntl; /* SDRAM Mode Control */
406 u32 sdram_interval; /* SDRAM Interval Configuration */
407 u32 ddr_data_init; /* SDRAM Data Initialization */
409 u32 sdram_clk_cntl; /* SDRAM Clock Control */
411 u32 ddr_init_addr; /* DDR training initialization address */
412 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
414 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
415 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
417 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
418 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
419 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
421 u32 capture_data_hi; /* Memory Data Path Read Capture High */
422 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
423 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
425 u32 err_detect; /* Memory Error Detect */
426 u32 err_disable; /* Memory Error Disable */
427 u32 err_int_en; /* Memory Error Interrupt Enable */
428 u32 capture_attributes; /* Memory Error Attributes Capture */
429 u32 capture_address; /* Memory Error Address Capture */
430 u32 capture_ext_address;/* Memory Error Extended Address Capture */
431 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
441 typedef struct duart83xx {
442 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
443 u8 uier_udmb; /* combined register for UIER and UDMB */
444 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
445 u8 ulcr; /* line control register */
446 u8 umcr; /* MODEM control register */
447 u8 ulsr; /* line status register */
448 u8 umsr; /* MODEM status register */
449 u8 uscr; /* scratch register */
451 u8 udsr; /* DMA status register */
459 typedef struct dma83xx {
460 u32 res0[0xC]; /* 0x0-0x29 reseverd */
461 u32 omisr; /* 0x30 Outbound message interrupt status register */
462 u32 omimr; /* 0x34 Outbound message interrupt mask register */
463 u32 res1[0x6]; /* 0x38-0x49 reserved */
464 u32 imr0; /* 0x50 Inbound message register 0 */
465 u32 imr1; /* 0x54 Inbound message register 1 */
466 u32 omr0; /* 0x58 Outbound message register 0 */
467 u32 omr1; /* 0x5C Outbound message register 1 */
468 u32 odr; /* 0x60 Outbound doorbell register */
469 u32 res2; /* 0x64-0x67 reserved */
470 u32 idr; /* 0x68 Inbound doorbell register */
471 u32 res3[0x5]; /* 0x6C-0x79 reserved */
472 u32 imisr; /* 0x80 Inbound message interrupt status register */
473 u32 imimr; /* 0x84 Inbound message interrupt mask register */
474 u32 res4[0x1E]; /* 0x88-0x99 reserved */
475 struct fsl_dma dma[4];
479 * PCI Software Configuration Registers
481 typedef struct pciconf83xx {
489 * PCI Outbound Translation Register
491 typedef struct pci_outbound_window {
503 typedef struct ios83xx {
513 * PCI Controller Control and Status Registers
515 typedef struct pcictrl83xx {
551 typedef struct usb83xx {
558 typedef struct tsec83xx {
565 typedef struct security83xx {
572 struct pex_inbound_window {
579 struct pex_outbound_window {
586 struct pex_csb_bridge {
617 u32 pex_int_apio_vec1;
618 u32 pex_int_apio_vec2;
620 u32 pex_int_ppio_vec1;
621 u32 pex_int_ppio_vec2;
622 u32 pex_int_wdma_vec1;
623 u32 pex_int_wdma_vec2;
624 u32 pex_int_rdma_vec1;
625 u32 pex_int_rdma_vec2;
626 u32 pex_int_misc_vec;
628 u32 pex_int_axi_pio_enb;
629 u32 pex_int_axi_wdma_enb;
630 u32 pex_int_axi_rdma_enb;
631 u32 pex_int_axi_misc_enb;
632 u32 pex_int_axi_pio_stat;
633 u32 pex_int_axi_wdma_stat;
634 u32 pex_int_axi_rdma_stat;
635 u32 pex_int_axi_misc_stat;
637 struct pex_outbound_window pex_outbound_win[4];
644 struct pex_inbound_window pex_inbound_win[4];
647 typedef struct pex83xx {
648 u8 pex_cfg_header[0x404];
651 u32 pex_ack_replay_timeout;
658 u32 pex_aspm_req_timer;
660 u32 pex_ssvid_update;
670 u32 pex_pme_to_ack_tor;
672 u32 pex_ss_intr_mask;
674 struct pex_csb_bridge bridge;
681 typedef struct sata83xx {
688 typedef struct sdhc83xx {
695 typedef struct serdes83xx {
709 typedef struct rom83xx {
716 typedef struct tdm83xx {
723 typedef struct tdmdmac83xx {
727 #if defined(CONFIG_MPC834x)
728 typedef struct immap {
729 sysconf83xx_t sysconf; /* System configuration */
730 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
731 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
732 rtclk83xx_t pit; /* Periodic Interval Timer */
733 gtm83xx_t gtm[2]; /* Global Timers Module */
734 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
735 arbiter83xx_t arbiter; /* System Arbiter Registers */
736 reset83xx_t reset; /* Reset Module */
737 clk83xx_t clk; /* System Clock Module */
738 pmc83xx_t pmc; /* Power Management Control Module */
739 gpio83xx_t gpio[2]; /* General purpose I/O module */
744 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
745 ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
747 ddr83xx_t ddr; /* DDR Memory Controller Memory */
749 fsl_i2c_t i2c[2]; /* I2C Controllers */
751 duart83xx_t duart[2]; /* DUART */
753 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
755 spi8xxx_t spi; /* Serial Peripheral Interface */
756 dma83xx_t dma; /* DMA */
757 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
758 ios83xx_t ios; /* Sequencer */
759 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
764 security83xx_t security;
768 #ifdef CONFIG_HAS_FSL_MPH_USB
769 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
771 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
774 #elif defined(CONFIG_MPC8313)
775 typedef struct immap {
776 sysconf83xx_t sysconf; /* System configuration */
777 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
778 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
779 rtclk83xx_t pit; /* Periodic Interval Timer */
780 gtm83xx_t gtm[2]; /* Global Timers Module */
781 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
782 arbiter83xx_t arbiter; /* System Arbiter Registers */
783 reset83xx_t reset; /* Reset Module */
784 clk83xx_t clk; /* System Clock Module */
785 pmc83xx_t pmc; /* Power Management Control Module */
786 gpio83xx_t gpio[1]; /* General purpose I/O module */
788 ddr83xx_t ddr; /* DDR Memory Controller Memory */
789 fsl_i2c_t i2c[2]; /* I2C Controllers */
791 duart83xx_t duart[2]; /* DUART */
793 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
795 spi8xxx_t spi; /* Serial Peripheral Interface */
796 dma83xx_t dma; /* DMA */
797 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
799 ios83xx_t ios; /* Sequencer */
800 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
805 security83xx_t security;
809 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
810 typedef struct immap {
811 sysconf83xx_t sysconf; /* System configuration */
812 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
813 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
814 rtclk83xx_t pit; /* Periodic Interval Timer */
815 gtm83xx_t gtm[2]; /* Global Timers Module */
816 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
817 arbiter83xx_t arbiter; /* System Arbiter Registers */
818 reset83xx_t reset; /* Reset Module */
819 clk83xx_t clk; /* System Clock Module */
820 pmc83xx_t pmc; /* Power Management Control Module */
821 gpio83xx_t gpio[1]; /* General purpose I/O module */
823 ddr83xx_t ddr; /* DDR Memory Controller Memory */
824 fsl_i2c_t i2c[2]; /* I2C Controllers */
826 duart83xx_t duart[2]; /* DUART */
828 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
830 spi8xxx_t spi; /* Serial Peripheral Interface */
831 dma83xx_t dma; /* DMA */
832 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
834 ios83xx_t ios; /* Sequencer */
835 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
837 pex83xx_t pciexp[2]; /* PCI Express Controller */
839 tdm83xx_t tdm; /* TDM Controller */
841 sata83xx_t sata[2]; /* SATA Controller */
843 usb83xx_t usb[1]; /* USB DR Controller */
846 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
848 security83xx_t security;
850 serdes83xx_t serdes[1]; /* SerDes Registers */
854 #elif defined(CONFIG_MPC837x)
855 typedef struct immap {
856 sysconf83xx_t sysconf; /* System configuration */
857 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
858 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
859 rtclk83xx_t pit; /* Periodic Interval Timer */
860 gtm83xx_t gtm[2]; /* Global Timers Module */
861 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
862 arbiter83xx_t arbiter; /* System Arbiter Registers */
863 reset83xx_t reset; /* Reset Module */
864 clk83xx_t clk; /* System Clock Module */
865 pmc83xx_t pmc; /* Power Management Control Module */
866 gpio83xx_t gpio[2]; /* General purpose I/O module */
868 ddr83xx_t ddr; /* DDR Memory Controller Memory */
869 fsl_i2c_t i2c[2]; /* I2C Controllers */
871 duart83xx_t duart[2]; /* DUART */
873 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
875 spi8xxx_t spi; /* Serial Peripheral Interface */
876 dma83xx_t dma; /* DMA */
877 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
879 ios83xx_t ios; /* Sequencer */
880 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
882 pex83xx_t pciexp[2]; /* PCI Express Controller */
884 sata83xx_t sata[4]; /* SATA Controller */
886 usb83xx_t usb[1]; /* USB DR Controller */
889 sdhc83xx_t sdhc; /* SDHC Controller */
891 security83xx_t security;
893 serdes83xx_t serdes[2]; /* SerDes Registers */
895 rom83xx_t rom; /* On Chip ROM */
898 #elif defined(CONFIG_MPC8360)
899 typedef struct immap {
900 sysconf83xx_t sysconf; /* System configuration */
901 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
902 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
903 rtclk83xx_t pit; /* Periodic Interval Timer */
905 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
906 arbiter83xx_t arbiter; /* System Arbiter Registers */
907 reset83xx_t reset; /* Reset Module */
908 clk83xx_t clk; /* System Clock Module */
909 pmc83xx_t pmc; /* Power Management Control Module */
910 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
915 qepio83xx_t qepio; /* QE Parallel I/O ports */
916 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
918 ddr83xx_t ddr; /* DDR Memory Controller Memory */
919 fsl_i2c_t i2c[2]; /* I2C Controllers */
921 duart83xx_t duart[2]; /* DUART */
923 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
925 dma83xx_t dma; /* DMA */
926 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
928 ios83xx_t ios; /* Sequencer (IOS) */
929 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
931 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
933 security83xx_t security;
935 u8 qe[0x100000]; /* QE block */
938 #elif defined(CONFIG_MPC832x)
939 typedef struct immap {
940 sysconf83xx_t sysconf; /* System configuration */
941 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
942 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
943 rtclk83xx_t pit; /* Periodic Interval Timer */
944 gtm83xx_t gtm[2]; /* Global Timers Module */
945 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
946 arbiter83xx_t arbiter; /* System Arbiter Registers */
947 reset83xx_t reset; /* Reset Module */
948 clk83xx_t clk; /* System Clock Module */
949 pmc83xx_t pmc; /* Power Management Control Module */
950 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
955 qepio83xx_t qepio; /* QE Parallel I/O ports */
957 ddr83xx_t ddr; /* DDR Memory Controller Memory */
958 fsl_i2c_t i2c[2]; /* I2C Controllers */
960 duart83xx_t duart[2]; /* DUART */
962 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
964 dma83xx_t dma; /* DMA */
965 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
967 ios83xx_t ios; /* Sequencer (IOS) */
968 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
970 security83xx_t security;
972 u8 qe[0x100000]; /* QE block */
976 #define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
977 #define CONFIG_SYS_MPC83xx_DDR_ADDR \
978 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
979 #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
980 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
981 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
982 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
983 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
984 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
986 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
987 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
989 #define CONFIG_SYS_MPC83xx_USB_ADDR \
990 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
991 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
993 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
994 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
996 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
997 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
998 #endif /* __IMMAP_83xx__ */