2 * MPC85xx Internal Memory Map
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_85xx__
29 #define __IMMAP_85xx__
31 #include <asm/types.h>
32 #include <asm/fsl_dma.h>
33 #include <asm/fsl_i2c.h>
34 #include <asm/fsl_lbc.h>
35 #include <asm/fsl_fman.h>
37 typedef struct ccsr_local {
38 u32 ccsrbarh; /* CCSR Base Addr High */
39 u32 ccsrbarl; /* CCSR Base Addr Low */
40 u32 ccsrar; /* CCSR Attr */
41 #define CCSRAR_C 0x80000000 /* Commit */
43 u32 altcbarh; /* Alternate Configuration Base Addr High */
44 u32 altcbarl; /* Alternate Configuration Base Addr Low */
45 u32 altcar; /* Alternate Configuration Attr */
47 u32 bstrh; /* Boot space translation high */
48 u32 bstrl; /* Boot space translation Low */
49 u32 bstrar; /* Boot space translation attributes */
52 u32 lawbarh; /* LAWn base addr high */
53 u32 lawbarl; /* LAWn base addr low */
54 u32 lawar; /* LAWn attributes */
60 /* Local-Access Registers & ECM Registers */
61 typedef struct ccsr_local_ecm {
62 u32 ccsrbar; /* CCSR Base Addr */
64 u32 altcbar; /* Alternate Configuration Base Addr */
66 u32 altcar; /* Alternate Configuration Attr */
68 u32 bptr; /* Boot Page Translation */
70 u32 lawbar0; /* Local Access Window 0 Base Addr */
72 u32 lawar0; /* Local Access Window 0 Attrs */
74 u32 lawbar1; /* Local Access Window 1 Base Addr */
76 u32 lawar1; /* Local Access Window 1 Attrs */
78 u32 lawbar2; /* Local Access Window 2 Base Addr */
80 u32 lawar2; /* Local Access Window 2 Attrs */
82 u32 lawbar3; /* Local Access Window 3 Base Addr */
84 u32 lawar3; /* Local Access Window 3 Attrs */
86 u32 lawbar4; /* Local Access Window 4 Base Addr */
88 u32 lawar4; /* Local Access Window 4 Attrs */
90 u32 lawbar5; /* Local Access Window 5 Base Addr */
92 u32 lawar5; /* Local Access Window 5 Attrs */
94 u32 lawbar6; /* Local Access Window 6 Base Addr */
96 u32 lawar6; /* Local Access Window 6 Attrs */
98 u32 lawbar7; /* Local Access Window 7 Base Addr */
100 u32 lawar7; /* Local Access Window 7 Attrs */
102 u32 lawbar8; /* Local Access Window 8 Base Addr */
104 u32 lawar8; /* Local Access Window 8 Attrs */
106 u32 lawbar9; /* Local Access Window 9 Base Addr */
108 u32 lawar9; /* Local Access Window 9 Attrs */
110 u32 lawbar10; /* Local Access Window 10 Base Addr */
112 u32 lawar10; /* Local Access Window 10 Attrs */
114 u32 lawbar11; /* Local Access Window 11 Base Addr */
116 u32 lawar11; /* Local Access Window 11 Attrs */
118 u32 eebacr; /* ECM CCB Addr Configuration */
120 u32 eebpcr; /* ECM CCB Port Configuration */
122 u32 eedr; /* ECM Error Detect */
124 u32 eeer; /* ECM Error Enable */
125 u32 eeatr; /* ECM Error Attrs Capture */
126 u32 eeadr; /* ECM Error Addr Capture */
130 /* DDR memory controller registers */
131 typedef struct ccsr_ddr {
132 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
134 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
136 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
138 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
140 u32 cs0_config; /* Chip Select Configuration */
141 u32 cs1_config; /* Chip Select Configuration */
142 u32 cs2_config; /* Chip Select Configuration */
143 u32 cs3_config; /* Chip Select Configuration */
145 u32 cs0_config_2; /* Chip Select Configuration 2 */
146 u32 cs1_config_2; /* Chip Select Configuration 2 */
147 u32 cs2_config_2; /* Chip Select Configuration 2 */
148 u32 cs3_config_2; /* Chip Select Configuration 2 */
150 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
151 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
152 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
153 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
154 u32 sdram_cfg; /* SDRAM Control Configuration */
155 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
156 u32 sdram_mode; /* SDRAM Mode Configuration */
157 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
158 u32 sdram_md_cntl; /* SDRAM Mode Control */
159 u32 sdram_interval; /* SDRAM Interval Configuration */
160 u32 sdram_data_init; /* SDRAM Data initialization */
162 u32 sdram_clk_cntl; /* SDRAM Clock Control */
164 u32 init_addr; /* training init addr */
165 u32 init_ext_addr; /* training init extended addr */
167 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
168 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
170 u32 ddr_zq_cntl; /* ZQ calibration control*/
171 u32 ddr_wrlvl_cntl; /* write leveling control*/
173 u32 ddr_sr_cntr; /* self refresh counter */
174 u32 ddr_sdram_rcw_1; /* Control Words 1 */
175 u32 ddr_sdram_rcw_2; /* Control Words 2 */
177 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
178 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
180 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
181 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
182 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
183 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
184 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
185 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
187 u32 ddr_dsr1; /* Debug Status 1 */
188 u32 ddr_dsr2; /* Debug Status 2 */
189 u32 ddr_cdr1; /* Control Driver 1 */
190 u32 ddr_cdr2; /* Control Driver 2 */
192 u32 ip_rev1; /* IP Block Revision 1 */
193 u32 ip_rev2; /* IP Block Revision 2 */
194 u32 eor; /* Enhanced Optimization Register */
196 u32 mtcr; /* Memory Test Control Register */
198 u32 mtp1; /* Memory Test Pattern 1 */
199 u32 mtp2; /* Memory Test Pattern 2 */
200 u32 mtp3; /* Memory Test Pattern 3 */
201 u32 mtp4; /* Memory Test Pattern 4 */
202 u32 mtp5; /* Memory Test Pattern 5 */
203 u32 mtp6; /* Memory Test Pattern 6 */
204 u32 mtp7; /* Memory Test Pattern 7 */
205 u32 mtp8; /* Memory Test Pattern 8 */
206 u32 mtp9; /* Memory Test Pattern 9 */
207 u32 mtp10; /* Memory Test Pattern 10 */
209 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
210 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
211 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
213 u32 capture_data_hi; /* Data Path Read Capture High */
214 u32 capture_data_lo; /* Data Path Read Capture Low */
215 u32 capture_ecc; /* Data Path Read Capture ECC */
217 u32 err_detect; /* Error Detect */
218 u32 err_disable; /* Error Disable */
220 u32 capture_attributes; /* Error Attrs Capture */
221 u32 capture_address; /* Error Addr Capture */
222 u32 capture_ext_address; /* Error Extended Addr Capture */
223 u32 err_sbe; /* Single-Bit ECC Error Management */
225 u32 debug[32]; /* debug_1 to debug_32 */
229 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
230 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
233 typedef struct ccsr_i2c {
234 struct fsl_i2c i2c[1];
235 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
238 #if defined(CONFIG_MPC8540) \
239 || defined(CONFIG_MPC8541) \
240 || defined(CONFIG_MPC8548) \
241 || defined(CONFIG_MPC8555)
242 /* DUART Registers */
243 typedef struct ccsr_duart {
245 /* URBR1, UTHR1, UDLB1 with the same addr */
246 u8 urbr1_uthr1_udlb1;
247 /* UIER1, UDMB1 with the same addr01 */
249 /* UIIR1, UFCR1, UAFR1 with the same addr */
250 u8 uiir1_ufcr1_uafr1;
251 u8 ulcr1; /* UART1 Line Control */
252 u8 umcr1; /* UART1 Modem Control */
253 u8 ulsr1; /* UART1 Line Status */
254 u8 umsr1; /* UART1 Modem Status */
255 u8 uscr1; /* UART1 Scratch */
257 u8 udsr1; /* UART1 DMA Status */
259 /* URBR2, UTHR2, UDLB2 with the same addr */
260 u8 urbr2_uthr2_udlb2;
261 /* UIER2, UDMB2 with the same addr */
263 /* UIIR2, UFCR2, UAFR2 with the same addr */
264 u8 uiir2_ufcr2_uafr2;
265 u8 ulcr2; /* UART2 Line Control */
266 u8 umcr2; /* UART2 Modem Control */
267 u8 ulsr2; /* UART2 Line Status */
268 u8 umsr2; /* UART2 Modem Status */
269 u8 uscr2; /* UART2 Scratch */
271 u8 udsr2; /* UART2 DMA Status */
274 #else /* MPC8560 uses UART on its CPM */
275 typedef struct ccsr_duart {
281 typedef struct ccsr_espi {
282 u32 mode; /* eSPI mode */
283 u32 event; /* eSPI event */
284 u32 mask; /* eSPI mask */
285 u32 com; /* eSPI command */
286 u32 tx; /* eSPI transmit FIFO access */
287 u32 rx; /* eSPI receive FIFO access */
288 u8 res1[8]; /* reserved */
289 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
290 u8 res2[4048]; /* fill up to 0x1000 */
294 typedef struct ccsr_pcix {
295 u32 cfg_addr; /* PCIX Configuration Addr */
296 u32 cfg_data; /* PCIX Configuration Data */
297 u32 int_ack; /* PCIX IRQ Acknowledge */
299 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
300 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
301 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
302 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
303 u32 powar0; /* PCIX Outbound Window Attrs 0 */
305 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
306 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
307 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
308 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
309 u32 powar1; /* PCIX Outbound Window Attrs 1 */
311 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
312 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
313 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
314 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
315 u32 powar2; /* PCIX Outbound Window Attrs 2 */
317 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
318 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
319 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
320 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
321 u32 powar3; /* PCIX Outbound Window Attrs 3 */
323 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
324 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
325 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
326 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
327 u32 powar4; /* PCIX Outbound Window Attrs 4 */
329 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
330 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
331 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
332 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
333 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
335 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
336 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
337 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
338 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
339 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
341 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
342 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
343 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
345 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
347 u32 pedr; /* PCIX Error Detect */
348 u32 pecdr; /* PCIX Error Capture Disable */
349 u32 peer; /* PCIX Error Enable */
350 u32 peattrcr; /* PCIX Error Attrs Capture */
351 u32 peaddrcr; /* PCIX Error Addr Capture */
352 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
353 u32 pedlcr; /* PCIX Error Data Low Capture */
354 u32 pedhcr; /* PCIX Error Error Data High Capture */
355 u32 gas_timr; /* PCIX Gasket Timer */
359 #define PCIX_COMMAND 0x62
360 #define POWAR_EN 0x80000000
361 #define POWAR_IO_READ 0x00080000
362 #define POWAR_MEM_READ 0x00040000
363 #define POWAR_IO_WRITE 0x00008000
364 #define POWAR_MEM_WRITE 0x00004000
365 #define POWAR_MEM_512M 0x0000001c
366 #define POWAR_IO_1M 0x00000013
368 #define PIWAR_EN 0x80000000
369 #define PIWAR_PF 0x20000000
370 #define PIWAR_LOCAL 0x00f00000
371 #define PIWAR_READ_SNOOP 0x00050000
372 #define PIWAR_WRITE_SNOOP 0x00005000
373 #define PIWAR_MEM_2G 0x0000001e
375 typedef struct ccsr_gpio {
384 /* L2 Cache Registers */
385 typedef struct ccsr_l2cache {
386 u32 l2ctl; /* L2 configuration 0 */
388 u32 l2cewar0; /* L2 cache external write addr 0 */
390 u32 l2cewcr0; /* L2 cache external write control 0 */
392 u32 l2cewar1; /* L2 cache external write addr 1 */
394 u32 l2cewcr1; /* L2 cache external write control 1 */
396 u32 l2cewar2; /* L2 cache external write addr 2 */
398 u32 l2cewcr2; /* L2 cache external write control 2 */
400 u32 l2cewar3; /* L2 cache external write addr 3 */
402 u32 l2cewcr3; /* L2 cache external write control 3 */
404 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
406 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
408 u32 l2errinjhi; /* L2 error injection mask high */
409 u32 l2errinjlo; /* L2 error injection mask low */
410 u32 l2errinjctl; /* L2 error injection tag/ECC control */
412 u32 l2captdatahi; /* L2 error data high capture */
413 u32 l2captdatalo; /* L2 error data low capture */
414 u32 l2captecc; /* L2 error ECC capture */
416 u32 l2errdet; /* L2 error detect */
417 u32 l2errdis; /* L2 error disable */
418 u32 l2errinten; /* L2 error interrupt enable */
419 u32 l2errattr; /* L2 error attributes capture */
420 u32 l2erraddr; /* L2 error addr capture */
422 u32 l2errctl; /* L2 error control */
426 #define MPC85xx_L2CTL_L2E 0x80000000
427 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
428 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
429 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
432 typedef struct ccsr_dma {
434 struct fsl_dma dma[4];
435 u32 dgsr; /* DMA General Status */
440 typedef struct ccsr_tsec {
442 u32 ievent; /* IRQ Event */
443 u32 imask; /* IRQ Mask */
444 u32 edis; /* Error Disabled */
446 u32 ecntrl; /* Ethernet Control */
447 u32 minflr; /* Minimum Frame Len */
448 u32 ptv; /* Pause Time Value */
449 u32 dmactrl; /* DMA Control */
450 u32 tbipa; /* TBI PHY Addr */
452 u32 fifo_tx_thr; /* FIFO transmit threshold */
454 u32 fifo_tx_starve; /* FIFO transmit starve */
455 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
457 u32 tctrl; /* TX Control */
458 u32 tstat; /* TX Status */
460 u32 tbdlen; /* TX Buffer Desc Data Len */
462 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
463 u32 ctbptr; /* Current TX Buffer Desc Ptr */
465 u32 tbptrh; /* TX Buffer Desc Ptr High */
466 u32 tbptr; /* TX Buffer Desc Ptr Low */
468 u32 tbaseh; /* TX Desc Base Addr High */
469 u32 tbase; /* TX Desc Base Addr */
471 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
472 u32 ostbdp; /* OOS TX Data Buffer Ptr */
473 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
474 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
475 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
476 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
477 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
479 u32 rctrl; /* RX Control */
480 u32 rstat; /* RX Status */
482 u32 rbdlen; /* RxBD Data Len */
484 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
485 u32 crbptr; /* Current RX Buffer Desc Ptr */
487 u32 mrblr; /* Maximum RX Buffer Len */
488 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
490 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
491 u32 rbptr; /* RX Buffer Desc Ptr */
492 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
493 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
494 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
495 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
496 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
497 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
499 u32 rbaseh; /* RX Desc Base Addr High 0 */
500 u32 rbase; /* RX Desc Base Addr */
501 u32 rbaseh1; /* RX Desc Base Addr High 1 */
502 u32 rbasel1; /* RX Desc Base Addr Low 1 */
503 u32 rbaseh2; /* RX Desc Base Addr High 2 */
504 u32 rbasel2; /* RX Desc Base Addr Low 2 */
505 u32 rbaseh3; /* RX Desc Base Addr High 3 */
506 u32 rbasel3; /* RX Desc Base Addr Low 3 */
508 u32 maccfg1; /* MAC Configuration 1 */
509 u32 maccfg2; /* MAC Configuration 2 */
510 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
511 u32 hafdup; /* Half Duplex */
512 u32 maxfrm; /* Maximum Frame Len */
514 u32 miimcfg; /* MII Management Configuration */
515 u32 miimcom; /* MII Management Cmd */
516 u32 miimadd; /* MII Management Addr */
517 u32 miimcon; /* MII Management Control */
518 u32 miimstat; /* MII Management Status */
519 u32 miimind; /* MII Management Indicator */
521 u32 ifstat; /* Interface Status */
522 u32 macstnaddr1; /* Station Addr Part 1 */
523 u32 macstnaddr2; /* Station Addr Part 2 */
525 u32 tr64; /* TX & RX 64-byte Frame Counter */
526 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
527 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
528 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
529 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
530 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
531 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
532 u32 rbyt; /* RX Byte Counter */
533 u32 rpkt; /* RX Packet Counter */
534 u32 rfcs; /* RX FCS Error Counter */
535 u32 rmca; /* RX Multicast Packet Counter */
536 u32 rbca; /* RX Broadcast Packet Counter */
537 u32 rxcf; /* RX Control Frame Packet Counter */
538 u32 rxpf; /* RX Pause Frame Packet Counter */
539 u32 rxuo; /* RX Unknown OP Code Counter */
540 u32 raln; /* RX Alignment Error Counter */
541 u32 rflr; /* RX Frame Len Error Counter */
542 u32 rcde; /* RX Code Error Counter */
543 u32 rcse; /* RX Carrier Sense Error Counter */
544 u32 rund; /* RX Undersize Packet Counter */
545 u32 rovr; /* RX Oversize Packet Counter */
546 u32 rfrg; /* RX Fragments Counter */
547 u32 rjbr; /* RX Jabber Counter */
548 u32 rdrp; /* RX Drop Counter */
549 u32 tbyt; /* TX Byte Counter Counter */
550 u32 tpkt; /* TX Packet Counter */
551 u32 tmca; /* TX Multicast Packet Counter */
552 u32 tbca; /* TX Broadcast Packet Counter */
553 u32 txpf; /* TX Pause Control Frame Counter */
554 u32 tdfr; /* TX Deferral Packet Counter */
555 u32 tedf; /* TX Excessive Deferral Packet Counter */
556 u32 tscl; /* TX Single Collision Packet Counter */
557 u32 tmcl; /* TX Multiple Collision Packet Counter */
558 u32 tlcl; /* TX Late Collision Packet Counter */
559 u32 txcl; /* TX Excessive Collision Packet Counter */
560 u32 tncl; /* TX Total Collision Counter */
562 u32 tdrp; /* TX Drop Frame Counter */
563 u32 tjbr; /* TX Jabber Frame Counter */
564 u32 tfcs; /* TX FCS Error Counter */
565 u32 txcf; /* TX Control Frame Counter */
566 u32 tovr; /* TX Oversize Frame Counter */
567 u32 tund; /* TX Undersize Frame Counter */
568 u32 tfrg; /* TX Fragments Frame Counter */
569 u32 car1; /* Carry One */
570 u32 car2; /* Carry Two */
571 u32 cam1; /* Carry Mask One */
572 u32 cam2; /* Carry Mask Two */
574 u32 iaddr0; /* Indivdual addr 0 */
575 u32 iaddr1; /* Indivdual addr 1 */
576 u32 iaddr2; /* Indivdual addr 2 */
577 u32 iaddr3; /* Indivdual addr 3 */
578 u32 iaddr4; /* Indivdual addr 4 */
579 u32 iaddr5; /* Indivdual addr 5 */
580 u32 iaddr6; /* Indivdual addr 6 */
581 u32 iaddr7; /* Indivdual addr 7 */
583 u32 gaddr0; /* Global addr 0 */
584 u32 gaddr1; /* Global addr 1 */
585 u32 gaddr2; /* Global addr 2 */
586 u32 gaddr3; /* Global addr 3 */
587 u32 gaddr4; /* Global addr 4 */
588 u32 gaddr5; /* Global addr 5 */
589 u32 gaddr6; /* Global addr 6 */
590 u32 gaddr7; /* Global addr 7 */
592 u32 pmd0; /* Pattern Match Data */
594 u32 pmask0; /* Pattern Mask */
596 u32 pcntrl0; /* Pattern Match Control */
598 u32 pattrb0; /* Pattern Match Attrs */
599 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
600 u32 pmd1; /* Pattern Match Data */
602 u32 pmask1; /* Pattern Mask */
604 u32 pcntrl1; /* Pattern Match Control */
606 u32 pattrb1; /* Pattern Match Attrs */
607 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
608 u32 pmd2; /* Pattern Match Data */
610 u32 pmask2; /* Pattern Mask */
612 u32 pcntrl2; /* Pattern Match Control */
614 u32 pattrb2; /* Pattern Match Attrs */
615 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
616 u32 pmd3; /* Pattern Match Data */
618 u32 pmask3; /* Pattern Mask */
620 u32 pcntrl3; /* Pattern Match Control */
622 u32 pattrb3; /* Pattern Match Attrs */
623 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
624 u32 pmd4; /* Pattern Match Data */
626 u32 pmask4; /* Pattern Mask */
628 u32 pcntrl4; /* Pattern Match Control */
630 u32 pattrb4; /* Pattern Match Attrs */
631 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
632 u32 pmd5; /* Pattern Match Data */
634 u32 pmask5; /* Pattern Mask */
636 u32 pcntrl5; /* Pattern Match Control */
638 u32 pattrb5; /* Pattern Match Attrs */
639 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
640 u32 pmd6; /* Pattern Match Data */
642 u32 pmask6; /* Pattern Mask */
644 u32 pcntrl6; /* Pattern Match Control */
646 u32 pattrb6; /* Pattern Match Attrs */
647 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
648 u32 pmd7; /* Pattern Match Data */
650 u32 pmask7; /* Pattern Mask */
652 u32 pcntrl7; /* Pattern Match Control */
654 u32 pattrb7; /* Pattern Match Attrs */
655 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
656 u32 pmd8; /* Pattern Match Data */
658 u32 pmask8; /* Pattern Mask */
660 u32 pcntrl8; /* Pattern Match Control */
662 u32 pattrb8; /* Pattern Match Attrs */
663 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
664 u32 pmd9; /* Pattern Match Data */
666 u32 pmask9; /* Pattern Mask */
668 u32 pcntrl9; /* Pattern Match Control */
670 u32 pattrb9; /* Pattern Match Attrs */
671 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
672 u32 pmd10; /* Pattern Match Data */
674 u32 pmask10; /* Pattern Mask */
676 u32 pcntrl10; /* Pattern Match Control */
678 u32 pattrb10; /* Pattern Match Attrs */
679 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
680 u32 pmd11; /* Pattern Match Data */
682 u32 pmask11; /* Pattern Mask */
684 u32 pcntrl11; /* Pattern Match Control */
686 u32 pattrb11; /* Pattern Match Attrs */
687 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
688 u32 pmd12; /* Pattern Match Data */
690 u32 pmask12; /* Pattern Mask */
692 u32 pcntrl12; /* Pattern Match Control */
694 u32 pattrb12; /* Pattern Match Attrs */
695 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
696 u32 pmd13; /* Pattern Match Data */
698 u32 pmask13; /* Pattern Mask */
700 u32 pcntrl13; /* Pattern Match Control */
702 u32 pattrb13; /* Pattern Match Attrs */
703 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
704 u32 pmd14; /* Pattern Match Data */
706 u32 pmask14; /* Pattern Mask */
708 u32 pcntrl14; /* Pattern Match Control */
710 u32 pattrb14; /* Pattern Match Attrs */
711 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
712 u32 pmd15; /* Pattern Match Data */
714 u32 pmask15; /* Pattern Mask */
716 u32 pcntrl15; /* Pattern Match Control */
718 u32 pattrb15; /* Pattern Match Attrs */
719 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
721 u32 attr; /* Attrs */
722 u32 attreli; /* Attrs Extract Len & Idx */
727 typedef struct ccsr_pic {
729 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
731 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
733 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
735 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
737 u32 ctpr; /* Current Task Priority */
739 u32 whoami; /* Who Am I */
741 u32 iack; /* IRQ Acknowledge */
743 u32 eoi; /* End Of IRQ */
745 u32 frr; /* Feature Reporting */
747 u32 gcr; /* Global Configuration */
748 #define MPC85xx_PICGCR_RST 0x80000000
749 #define MPC85xx_PICGCR_M 0x20000000
751 u32 vir; /* Vendor Identification */
753 u32 pir; /* Processor Initialization */
755 u32 ipivpr0; /* IPI Vector/Priority 0 */
757 u32 ipivpr1; /* IPI Vector/Priority 1 */
759 u32 ipivpr2; /* IPI Vector/Priority 2 */
761 u32 ipivpr3; /* IPI Vector/Priority 3 */
763 u32 svr; /* Spurious Vector */
765 u32 tfrr; /* Timer Frequency Reporting */
767 u32 gtccr0; /* Global Timer Current Count 0 */
769 u32 gtbcr0; /* Global Timer Base Count 0 */
771 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
773 u32 gtdr0; /* Global Timer Destination 0 */
775 u32 gtccr1; /* Global Timer Current Count 1 */
777 u32 gtbcr1; /* Global Timer Base Count 1 */
779 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
781 u32 gtdr1; /* Global Timer Destination 1 */
783 u32 gtccr2; /* Global Timer Current Count 2 */
785 u32 gtbcr2; /* Global Timer Base Count 2 */
787 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
789 u32 gtdr2; /* Global Timer Destination 2 */
791 u32 gtccr3; /* Global Timer Current Count 3 */
793 u32 gtbcr3; /* Global Timer Base Count 3 */
795 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
797 u32 gtdr3; /* Global Timer Destination 3 */
799 u32 tcr; /* Timer Control */
801 u32 irqsr0; /* IRQ_OUT Summary 0 */
803 u32 irqsr1; /* IRQ_OUT Summary 1 */
805 u32 cisr0; /* Critical IRQ Summary 0 */
807 u32 cisr1; /* Critical IRQ Summary 1 */
809 u32 msgr0; /* Message 0 */
811 u32 msgr1; /* Message 1 */
813 u32 msgr2; /* Message 2 */
815 u32 msgr3; /* Message 3 */
817 u32 mer; /* Message Enable */
819 u32 msr; /* Message Status */
821 u32 eivpr0; /* External IRQ Vector/Priority 0 */
823 u32 eidr0; /* External IRQ Destination 0 */
825 u32 eivpr1; /* External IRQ Vector/Priority 1 */
827 u32 eidr1; /* External IRQ Destination 1 */
829 u32 eivpr2; /* External IRQ Vector/Priority 2 */
831 u32 eidr2; /* External IRQ Destination 2 */
833 u32 eivpr3; /* External IRQ Vector/Priority 3 */
835 u32 eidr3; /* External IRQ Destination 3 */
837 u32 eivpr4; /* External IRQ Vector/Priority 4 */
839 u32 eidr4; /* External IRQ Destination 4 */
841 u32 eivpr5; /* External IRQ Vector/Priority 5 */
843 u32 eidr5; /* External IRQ Destination 5 */
845 u32 eivpr6; /* External IRQ Vector/Priority 6 */
847 u32 eidr6; /* External IRQ Destination 6 */
849 u32 eivpr7; /* External IRQ Vector/Priority 7 */
851 u32 eidr7; /* External IRQ Destination 7 */
853 u32 eivpr8; /* External IRQ Vector/Priority 8 */
855 u32 eidr8; /* External IRQ Destination 8 */
857 u32 eivpr9; /* External IRQ Vector/Priority 9 */
859 u32 eidr9; /* External IRQ Destination 9 */
861 u32 eivpr10; /* External IRQ Vector/Priority 10 */
863 u32 eidr10; /* External IRQ Destination 10 */
865 u32 eivpr11; /* External IRQ Vector/Priority 11 */
867 u32 eidr11; /* External IRQ Destination 11 */
869 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
871 u32 iidr0; /* Internal IRQ Destination 0 */
873 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
875 u32 iidr1; /* Internal IRQ Destination 1 */
877 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
879 u32 iidr2; /* Internal IRQ Destination 2 */
881 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
883 u32 iidr3; /* Internal IRQ Destination 3 */
885 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
887 u32 iidr4; /* Internal IRQ Destination 4 */
889 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
891 u32 iidr5; /* Internal IRQ Destination 5 */
893 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
895 u32 iidr6; /* Internal IRQ Destination 6 */
897 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
899 u32 iidr7; /* Internal IRQ Destination 7 */
901 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
903 u32 iidr8; /* Internal IRQ Destination 8 */
905 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
907 u32 iidr9; /* Internal IRQ Destination 9 */
909 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
911 u32 iidr10; /* Internal IRQ Destination 10 */
913 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
915 u32 iidr11; /* Internal IRQ Destination 11 */
917 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
919 u32 iidr12; /* Internal IRQ Destination 12 */
921 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
923 u32 iidr13; /* Internal IRQ Destination 13 */
925 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
927 u32 iidr14; /* Internal IRQ Destination 14 */
929 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
931 u32 iidr15; /* Internal IRQ Destination 15 */
933 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
935 u32 iidr16; /* Internal IRQ Destination 16 */
937 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
939 u32 iidr17; /* Internal IRQ Destination 17 */
941 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
943 u32 iidr18; /* Internal IRQ Destination 18 */
945 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
947 u32 iidr19; /* Internal IRQ Destination 19 */
949 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
951 u32 iidr20; /* Internal IRQ Destination 20 */
953 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
955 u32 iidr21; /* Internal IRQ Destination 21 */
957 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
959 u32 iidr22; /* Internal IRQ Destination 22 */
961 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
963 u32 iidr23; /* Internal IRQ Destination 23 */
965 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
967 u32 iidr24; /* Internal IRQ Destination 24 */
969 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
971 u32 iidr25; /* Internal IRQ Destination 25 */
973 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
975 u32 iidr26; /* Internal IRQ Destination 26 */
977 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
979 u32 iidr27; /* Internal IRQ Destination 27 */
981 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
983 u32 iidr28; /* Internal IRQ Destination 28 */
985 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
987 u32 iidr29; /* Internal IRQ Destination 29 */
989 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
991 u32 iidr30; /* Internal IRQ Destination 30 */
993 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
995 u32 iidr31; /* Internal IRQ Destination 31 */
997 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
999 u32 midr0; /* Messaging IRQ Destination 0 */
1001 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
1003 u32 midr1; /* Messaging IRQ Destination 1 */
1005 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
1007 u32 midr2; /* Messaging IRQ Destination 2 */
1009 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
1011 u32 midr3; /* Messaging IRQ Destination 3 */
1013 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1015 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1017 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1019 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1021 u32 ctpr0; /* Current Task Priority for Processor 0 */
1023 u32 whoami0; /* Who Am I for Processor 0 */
1025 u32 iack0; /* IRQ Acknowledge for Processor 0 */
1027 u32 eoi0; /* End Of IRQ for Processor 0 */
1033 typedef struct ccsr_cpm {
1041 typedef struct ccsr_cpm_siu {
1053 /* IRQ Controller */
1054 typedef struct ccsr_cpm_intctl {
1069 } ccsr_cpm_intctl_t;
1071 /* input/output port */
1072 typedef struct ccsr_cpm_iop {
1100 typedef struct ccsr_cpm_timer {
1129 typedef struct ccsr_cpm_sdma {
1137 typedef struct ccsr_cpm_fcc1 {
1154 typedef struct ccsr_cpm_fcc2 {
1171 typedef struct ccsr_cpm_fcc3 {
1188 typedef struct ccsr_cpm_fcc1_ext {
1196 } ccsr_cpm_fcc1_ext_t;
1199 typedef struct ccsr_cpm_fcc2_ext {
1206 } ccsr_cpm_fcc2_ext_t;
1209 typedef struct ccsr_cpm_fcc3_ext {
1212 } ccsr_cpm_fcc3_ext_t;
1215 typedef struct ccsr_cpm_tmp1 {
1220 typedef struct ccsr_cpm_brg2 {
1229 typedef struct ccsr_cpm_i2c {
1245 typedef struct ccsr_cpm_cp {
1259 typedef struct ccsr_cpm_brg1 {
1267 typedef struct ccsr_cpm_scc {
1282 typedef struct ccsr_cpm_tmp2 {
1287 typedef struct ccsr_cpm_spi {
1299 typedef struct ccsr_cpm_mux {
1312 typedef struct ccsr_cpm_tmp3 {
1316 typedef struct ccsr_cpm_iram {
1321 typedef struct ccsr_cpm {
1322 /* Some references are into the unique & known dpram spaces,
1323 * others are from the generic base.
1325 #define im_dprambase im_dpram1
1326 u8 im_dpram1[16*1024];
1328 u8 im_dpram2[16*1024];
1330 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1331 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1332 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1333 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1334 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1335 ccsr_cpm_fcc1_t im_cpm_fcc1;
1336 ccsr_cpm_fcc2_t im_cpm_fcc2;
1337 ccsr_cpm_fcc3_t im_cpm_fcc3;
1338 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1339 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1340 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1341 ccsr_cpm_tmp1_t im_cpm_tmp1;
1342 ccsr_cpm_brg2_t im_cpm_brg2;
1343 ccsr_cpm_i2c_t im_cpm_i2c;
1344 ccsr_cpm_cp_t im_cpm_cp;
1345 ccsr_cpm_brg1_t im_cpm_brg1;
1346 ccsr_cpm_scc_t im_cpm_scc[4];
1347 ccsr_cpm_tmp2_t im_cpm_tmp2;
1348 ccsr_cpm_spi_t im_cpm_spi;
1349 ccsr_cpm_mux_t im_cpm_mux;
1350 ccsr_cpm_tmp3_t im_cpm_tmp3;
1351 ccsr_cpm_iram_t im_cpm_iram;
1355 /* RapidIO Registers */
1356 typedef struct ccsr_rio {
1357 u32 didcar; /* Device Identity Capability */
1358 u32 dicar; /* Device Information Capability */
1359 u32 aidcar; /* Assembly Identity Capability */
1360 u32 aicar; /* Assembly Information Capability */
1361 u32 pefcar; /* Processing Element Features Capability */
1362 u32 spicar; /* Switch Port Information Capability */
1363 u32 socar; /* Source Operations Capability */
1364 u32 docar; /* Destination Operations Capability */
1366 u32 msr; /* Mailbox Cmd And Status */
1367 u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */
1369 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1371 u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */
1372 u32 bdidcsr; /* Base Device ID Cmd & Status */
1374 u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */
1375 u32 ctcsr; /* Component Tag Cmd & Status */
1377 u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */
1379 u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */
1380 u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */
1382 u32 pgccsr; /* Port General Cmd & Status */
1383 u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */
1384 u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */
1385 u32 plascsr; /* Port Local Ackid Status Cmd & Status */
1387 u32 pescsr; /* Port Error & Status Cmd & Status */
1388 u32 pccsr; /* Port Control Cmd & Status */
1390 u32 cr; /* Port Control Cmd & Status */
1392 u32 pcr; /* Port Configuration */
1393 u32 peir; /* Port Error Injection */
1395 u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */
1397 u32 rowar0; /* RIO Outbound Attrs 0 */
1399 u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */
1401 u32 rowbar1; /* RIO Outbound Window Base Addr 1 */
1403 u32 rowar1; /* RIO Outbound Attrs 1 */
1405 u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */
1407 u32 rowbar2; /* RIO Outbound Window Base Addr 2 */
1409 u32 rowar2; /* RIO Outbound Attrs 2 */
1411 u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */
1413 u32 rowbar3; /* RIO Outbound Window Base Addr 3 */
1415 u32 rowar3; /* RIO Outbound Attrs 3 */
1417 u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */
1419 u32 rowbar4; /* RIO Outbound Window Base Addr 4 */
1421 u32 rowar4; /* RIO Outbound Attrs 4 */
1423 u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */
1425 u32 rowbar5; /* RIO Outbound Window Base Addr 5 */
1427 u32 rowar5; /* RIO Outbound Attrs 5 */
1429 u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */
1431 u32 rowbar6; /* RIO Outbound Window Base Addr 6 */
1433 u32 rowar6; /* RIO Outbound Attrs 6 */
1435 u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */
1437 u32 rowbar7; /* RIO Outbound Window Base Addr 7 */
1439 u32 rowar7; /* RIO Outbound Attrs 7 */
1441 u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */
1443 u32 rowbar8; /* RIO Outbound Window Base Addr 8 */
1445 u32 rowar8; /* RIO Outbound Attrs 8 */
1447 u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */
1449 u32 riwbar4; /* RIO Inbound Window Base Addr 4 */
1451 u32 riwar4; /* RIO Inbound Attrs 4 */
1453 u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */
1455 u32 riwbar3; /* RIO Inbound Window Base Addr 3 */
1457 u32 riwar3; /* RIO Inbound Attrs 3 */
1459 u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */
1461 u32 riwbar2; /* RIO Inbound Window Base Addr 2 */
1463 u32 riwar2; /* RIO Inbound Attrs 2 */
1465 u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */
1467 u32 riwbar1; /* RIO Inbound Window Base Addr 1 */
1469 u32 riwar1; /* RIO Inbound Attrs 1 */
1471 u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */
1473 u32 riwar0; /* RIO Inbound Attrs 0 */
1475 u32 pnfedr; /* Port Notification/Fatal Error Detect */
1476 u32 pnfedir; /* Port Notification/Fatal Error Detect */
1477 u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */
1478 u32 pecr; /* Port Error Control */
1479 u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */
1480 u32 pepr1; /* Port Error Packet 1 */
1481 u32 pepr2; /* Port Error Packet 2 */
1483 u32 predr; /* Port Recoverable Error Detect */
1485 u32 pertr; /* Port Error Recovery Threshold */
1486 u32 prtr; /* Port Retry Threshold */
1488 u32 omr; /* Outbound Mode */
1489 u32 osr; /* Outbound Status */
1490 u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */
1491 u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */
1492 u32 eosar; /* Extended Outbound Unit Source Addr */
1493 u32 osar; /* Outbound Unit Source Addr */
1494 u32 odpr; /* Outbound Destination Port */
1495 u32 odatr; /* Outbound Destination Attrs */
1496 u32 odcr; /* Outbound Doubleword Count */
1497 u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */
1498 u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */
1500 u32 imr; /* Outbound Mode */
1501 u32 isr; /* Inbound Status */
1502 u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */
1503 u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */
1504 u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */
1505 u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */
1507 u32 dmr; /* Doorbell Mode */
1508 u32 dsr; /* Doorbell Status */
1509 u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */
1510 u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */
1511 u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */
1512 u32 dqhpar; /* Doorbell Queue Head Ptr Addr */
1514 u32 pwmr; /* Port-Write Mode */
1515 u32 pwsr; /* Port-Write Status */
1516 u32 epwqbar; /* Extended Port-Write Queue Base Addr */
1517 u32 pwqbar; /* Port-Write Queue Base Addr */
1521 /* Quick Engine Block Pin Muxing Registers */
1522 typedef struct par_io {
1532 #ifdef CONFIG_SYS_FSL_CPC
1534 * Define a single offset that is the start of all the CPC register
1535 * blocks - if there is more than one CPC, we expect these to be
1536 * contiguous 4k regions
1539 typedef struct cpc_corenet {
1540 u32 cpccsr0; /* Config/status reg */
1542 u32 cpccfg0; /* Configuration register */
1544 u32 cpcewcr0; /* External Write reg 0 */
1545 u32 cpcewabr0; /* External write base reg 0 */
1547 u32 cpcewcr1; /* External Write reg 1 */
1548 u32 cpcewabr1; /* External write base reg 1 */
1550 u32 cpcsrcr1; /* SRAM control reg 1 */
1551 u32 cpcsrcr0; /* SRAM control reg 0 */
1554 u32 id; /* partition ID */
1556 u32 alloc; /* partition allocation */
1557 u32 way; /* partition way */
1558 } partition_regs[16];
1560 u32 cpcerrinjhi; /* Error injection high */
1561 u32 cpcerrinjlo; /* Error injection lo */
1562 u32 cpcerrinjctl; /* Error injection control */
1564 u32 cpccaptdatahi; /* capture data high */
1565 u32 cpccaptdatalo; /* capture data low */
1566 u32 cpcaptecc; /* capture ECC */
1568 u32 cpcerrdet; /* error detect */
1569 u32 cpcerrdis; /* error disable */
1570 u32 cpcerrinten; /* errir interrupt enable */
1571 u32 cpcerrattr; /* error attribute */
1572 u32 cpcerreaddr; /* error extended address */
1573 u32 cpcerraddr; /* error address */
1574 u32 cpcerrctl; /* error control */
1575 u32 res9[41]; /* pad out to 4k */
1576 u32 cpchdbcr0; /* hardware debug control register 0 */
1577 u32 res10[63]; /* pad out to 4k */
1580 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1581 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1582 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1583 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1584 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1585 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1586 #define CPC_CFG0_SZ_MASK 0x00003fff
1587 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1588 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1589 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1590 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1591 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1592 & CPC_SRCR1_SRBARU_MASK)
1593 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1594 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1595 #define CPC_SRCR0_INTLVEN 0x00000100
1596 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1597 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1598 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1599 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1600 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1601 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1602 #define CPC_SRCR0_SRAMEN 0x00000001
1603 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1604 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1605 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1606 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1607 #endif /* CONFIG_SYS_FSL_CPC */
1609 /* Global Utilities Block */
1610 #ifdef CONFIG_FSL_CORENET
1611 typedef struct ccsr_gur {
1612 u32 porsr1; /* POR status */
1614 u32 gpporcr1; /* General-purpose POR configuration */
1616 u32 gpiocr; /* GPIO control */
1618 u32 gpoutdr; /* General-purpose output data */
1620 u32 gpindr; /* General-purpose input data */
1622 u32 alt_pmuxcr; /* Alt function signal multiplex control */
1624 u32 devdisr; /* Device disable control */
1625 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1626 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1627 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1628 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1629 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1630 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1631 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1632 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1633 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1634 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1635 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1636 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1637 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1638 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1639 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1640 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1641 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1642 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1643 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1644 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1645 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1646 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1647 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1648 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1649 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1650 u32 devdisr2; /* Device disable control 2 */
1651 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1652 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1653 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1654 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1655 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1656 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1657 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1658 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1659 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1660 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1661 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1662 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1663 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1664 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1665 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1666 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1667 #define FSL_CORENET_NUM_DEVDISR 2
1669 u32 powmgtcsr; /* Power management status & control */
1671 u32 coredisru; /* uppper portion for support of 64 cores */
1672 u32 coredisrl; /* lower portion for support of 64 cores */
1674 u32 pvr; /* Processor version */
1675 u32 svr; /* System version */
1677 u32 rstcr; /* Reset control */
1678 u32 rstrqpblsr; /* Reset request preboot loader status */
1680 u32 rstrqmr1; /* Reset request mask */
1682 u32 rstrqsr1; /* Reset request status */
1685 u32 rstrqwdtmrl; /* Reset request WDT mask */
1687 u32 rstrqwdtsrl; /* Reset request WDT status */
1689 u32 brrl; /* Boot release */
1691 u32 rcwsr[16]; /* Reset control word status */
1692 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1693 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1694 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1695 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1696 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1697 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1698 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1699 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1700 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1701 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1702 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1703 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1704 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1705 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1706 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1707 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1709 u32 scratchrw[4]; /* Scratch Read/Write */
1711 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1713 u32 scrtsr[8]; /* Core reset status */
1715 u32 pex1liodnr; /* PCI Express 1 LIODN */
1716 u32 pex2liodnr; /* PCI Express 2 LIODN */
1717 u32 pex3liodnr; /* PCI Express 3 LIODN */
1718 u32 pex4liodnr; /* PCI Express 4 LIODN */
1719 u32 rio1liodnr; /* RIO 1 LIODN */
1720 u32 rio2liodnr; /* RIO 2 LIODN */
1721 u32 rio3liodnr; /* RIO 3 LIODN */
1722 u32 rio4liodnr; /* RIO 4 LIODN */
1723 u32 usb1liodnr; /* USB 1 LIODN */
1724 u32 usb2liodnr; /* USB 2 LIODN */
1725 u32 usb3liodnr; /* USB 3 LIODN */
1726 u32 usb4liodnr; /* USB 4 LIODN */
1727 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1728 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1729 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1730 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1731 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1732 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1733 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1734 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1735 u32 sata1liodnr; /* SATA 1 LIODN */
1736 u32 sata2liodnr; /* SATA 2 LIODN */
1737 u32 sata3liodnr; /* SATA 3 LIODN */
1738 u32 sata4liodnr; /* SATA 4 LIODN */
1740 u32 dma1liodnr; /* DMA 1 LIODN */
1741 u32 dma2liodnr; /* DMA 2 LIODN */
1742 u32 dma3liodnr; /* DMA 3 LIODN */
1743 u32 dma4liodnr; /* DMA 4 LIODN */
1746 u32 pblsr; /* Preboot loader status */
1747 u32 pamubypenr; /* PAMU bypass enable */
1748 u32 dmacr1; /* DMA control */
1750 u32 gensr1; /* General status */
1752 u32 gencr1; /* General control */
1755 u32 cgensrl; /* Core general status */
1758 u32 cgencrl; /* Core general control */
1760 u32 sriopstecr; /* SRIO prescaler timer enable control */
1762 u32 pmuxcr; /* Pin multiplexing control */
1764 u32 iovselsr; /* I/O voltage selection status */
1766 u32 ddrclkdr; /* DDR clock disable */
1768 u32 elbcclkdr; /* eLBC clock disable */
1770 u32 sdhcpcr; /* eSDHC polarity configuration */
1775 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1776 * everything after has RMan thus msg unit LIODN is used for maintenance
1778 #define rmuliodnr rio1maintliodnr
1780 typedef struct ccsr_clk {
1781 u32 clkc0csr; /* Core 0 Clock control/status */
1783 u32 clkc1csr; /* Core 1 Clock control/status */
1785 u32 clkc2csr; /* Core 2 Clock control/status */
1787 u32 clkc3csr; /* Core 3 Clock control/status */
1789 u32 clkc4csr; /* Core 4 Clock control/status */
1791 u32 clkc5csr; /* Core 5 Clock control/status */
1793 u32 clkc6csr; /* Core 6 Clock control/status */
1795 u32 clkc7csr; /* Core 7 Clock control/status */
1797 u32 pllc1gsr; /* Cluster PLL 1 General Status */
1799 u32 pllc2gsr; /* Cluster PLL 2 General Status */
1801 u32 pllc3gsr; /* Cluster PLL 3 General Status */
1803 u32 pllc4gsr; /* Cluster PLL 4 General Status */
1805 u32 pllpgsr; /* Platform PLL General Status */
1807 u32 plldgsr; /* DDR PLL General Status */
1811 typedef struct ccsr_rcpm {
1813 u32 cdozsrl; /* Core Doze Status */
1815 u32 cdozcrl; /* Core Doze Control */
1817 u32 cnapsrl; /* Core Nap Status */
1819 u32 cnapcrl; /* Core Nap Control */
1821 u32 cdozpsrl; /* Core Doze Previous Status */
1823 u32 cdozpcrl; /* Core Doze Previous Control */
1825 u32 cwaitsrl; /* Core Wait Status */
1827 u32 powmgtcsr; /* Power Mangement Control & Status */
1829 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
1832 u32 cpmimrl; /* Core PM IRQ Masking */
1834 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
1836 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
1838 u32 cpmnmimrl; /* Core PM NMI Masking */
1840 u32 ctbenrl; /* Core Time Base Enable */
1842 u32 ctbclkselrl; /* Core Time Base Clock Select */
1844 u32 ctbhltcrl; /* Core Time Base Halt Control */
1849 typedef struct ccsr_gur {
1850 u32 porpllsr; /* POR PLL ratio status */
1851 #ifdef CONFIG_MPC8536
1852 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1853 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1855 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1856 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1858 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1859 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
1860 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
1861 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
1862 u32 porbmsr; /* POR boot mode status */
1863 #define MPC85xx_PORBMSR_HA 0x00070000
1864 #define MPC85xx_PORBMSR_HA_SHIFT 16
1865 u32 porimpscr; /* POR I/O impedance status & control */
1866 u32 pordevsr; /* POR I/O device status regsiter */
1867 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1868 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1869 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1870 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
1871 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
1872 #define MPC85xx_PORDEVSR_PCI1 0x00800000
1873 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
1874 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
1875 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
1877 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
1878 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
1880 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1881 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1882 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1883 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1884 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
1885 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
1886 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
1887 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
1888 u32 pordbgmsr; /* POR debug mode status */
1889 u32 pordevsr2; /* POR I/O device status 2 */
1890 /* The 8544 RM says this is bit 26, but it's really bit 24 */
1891 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
1893 u32 gpporcr; /* General-purpose POR configuration */
1895 u32 gpiocr; /* GPIO control */
1897 #if defined(CONFIG_MPC8569)
1898 u32 plppar1; /* Platform port pin assignment 1 */
1899 u32 plppar2; /* Platform port pin assignment 2 */
1900 u32 plpdir1; /* Platform port pin direction 1 */
1901 u32 plpdir2; /* Platform port pin direction 2 */
1903 u32 gpoutdr; /* General-purpose output data */
1906 u32 gpindr; /* General-purpose input data */
1908 u32 pmuxcr; /* Alt. function signal multiplex control */
1909 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
1910 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1911 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
1912 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
1914 u32 devdisr; /* Device disable control */
1915 #define MPC85xx_DEVDISR_PCI1 0x80000000
1916 #define MPC85xx_DEVDISR_PCI2 0x40000000
1917 #define MPC85xx_DEVDISR_PCIE 0x20000000
1918 #define MPC85xx_DEVDISR_LBC 0x08000000
1919 #define MPC85xx_DEVDISR_PCIE2 0x04000000
1920 #define MPC85xx_DEVDISR_PCIE3 0x02000000
1921 #define MPC85xx_DEVDISR_SEC 0x01000000
1922 #define MPC85xx_DEVDISR_SRIO 0x00080000
1923 #define MPC85xx_DEVDISR_RMSG 0x00040000
1924 #define MPC85xx_DEVDISR_DDR 0x00010000
1925 #define MPC85xx_DEVDISR_CPU 0x00008000
1926 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1927 #define MPC85xx_DEVDISR_TB 0x00004000
1928 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1929 #define MPC85xx_DEVDISR_CPU1 0x00002000
1930 #define MPC85xx_DEVDISR_TB1 0x00001000
1931 #define MPC85xx_DEVDISR_DMA 0x00000400
1932 #define MPC85xx_DEVDISR_TSEC1 0x00000080
1933 #define MPC85xx_DEVDISR_TSEC2 0x00000040
1934 #define MPC85xx_DEVDISR_TSEC3 0x00000020
1935 #define MPC85xx_DEVDISR_TSEC4 0x00000010
1936 #define MPC85xx_DEVDISR_I2C 0x00000004
1937 #define MPC85xx_DEVDISR_DUART 0x00000002
1939 u32 powmgtcsr; /* Power management status & control */
1941 u32 mcpsumr; /* Machine check summary */
1943 u32 pvr; /* Processor version */
1944 u32 svr; /* System version */
1946 u32 rstcr; /* Reset control */
1947 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
1949 par_io_t qe_par_io[7];
1954 u32 clkdvdr; /* Clock Divide register */
1956 u32 clkocr; /* Clock out select */
1958 u32 ddrdllcr; /* DDR DLL control */
1960 u32 lbcdllcr; /* LBC DLL control */
1962 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
1963 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
1964 u32 ddrioovcr; /* DDR IO Override Control */
1965 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
1966 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
1971 typedef struct serdes_corenet {
1973 u32 rstctl; /* Reset Control Register */
1974 #define SRDS_RSTCTL_RST 0x80000000
1975 #define SRDS_RSTCTL_RSTDONE 0x40000000
1976 #define SRDS_RSTCTL_RSTERR 0x20000000
1977 #define SRDS_RSTCTL_SDPD 0x00000020
1978 u32 pllcr0; /* PLL Control Register 0 */
1979 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
1980 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
1981 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
1982 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
1983 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
1984 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
1985 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
1986 u32 pllcr1; /* PLL Control Register 1 */
1987 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
1991 u32 srdstcalcr; /* TX Calibration Control */
1993 u32 srdsrcalcr; /* RX Calibration Control */
1995 u32 srdsgr0; /* General Register 0 */
1997 u32 srdspccr0; /* Protocol Converter Config 0 */
1998 u32 srdspccr1; /* Protocol Converter Config 1 */
1999 u32 srdspccr2; /* Protocol Converter Config 2 */
2000 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2001 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2004 u32 gcr0; /* General Control Register 0 */
2005 #define SRDS_GCR0_RRST 0x00400000
2006 #define SRDS_GCR0_1STLANE 0x00010000
2007 u32 gcr1; /* General Control Register 1 */
2008 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2009 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2010 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2011 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2012 #define SRDS_GCR1_OPAD_CTL 0x04000000
2014 u32 tecr0; /* TX Equalization Control Reg 0 */
2015 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2016 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2018 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2025 FSL_SRDS_B1_LANE_A = 0,
2026 FSL_SRDS_B1_LANE_B = 1,
2027 FSL_SRDS_B1_LANE_C = 2,
2028 FSL_SRDS_B1_LANE_D = 3,
2029 FSL_SRDS_B1_LANE_E = 4,
2030 FSL_SRDS_B1_LANE_F = 5,
2031 FSL_SRDS_B1_LANE_G = 6,
2032 FSL_SRDS_B1_LANE_H = 7,
2033 FSL_SRDS_B1_LANE_I = 8,
2034 FSL_SRDS_B1_LANE_J = 9,
2035 FSL_SRDS_B2_LANE_A = 16,
2036 FSL_SRDS_B2_LANE_B = 17,
2037 FSL_SRDS_B2_LANE_C = 18,
2038 FSL_SRDS_B2_LANE_D = 19,
2039 FSL_SRDS_B3_LANE_A = 20,
2040 FSL_SRDS_B3_LANE_B = 21,
2041 FSL_SRDS_B3_LANE_C = 22,
2042 FSL_SRDS_B3_LANE_D = 23,
2045 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2046 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2047 typedef struct ccsr_sec {
2049 u32 mcfgr; /* Master CFG Register */
2052 u32 ms; /* Job Ring LIODN Register, MS */
2053 u32 ls; /* Job Ring LIODN Register, LS */
2057 u32 ms; /* RTIC LIODN Register, MS */
2058 u32 ls; /* RTIC LIODN Register, LS */
2061 u32 decorr; /* DECO Request Register */
2063 u32 ms; /* DECO LIODN Register, MS */
2064 u32 ls; /* DECO LIODN Register, LS */
2067 u32 dar; /* DECO Avail Register */
2068 u32 drr; /* DECO Reset Register */
2070 u32 crnr_ms; /* CHA Revision Number Register, MS */
2071 u32 crnr_ls; /* CHA Revision Number Register, LS */
2072 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
2073 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
2075 u32 far_ms; /* Fault Address Register, MS */
2076 u32 far_ls; /* Fault Address Register, LS */
2077 u32 falr; /* Fault Address LIODN Register */
2078 u32 fadr; /* Fault Address Detail Register */
2080 u32 csta; /* CAAM Status Register */
2082 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
2083 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2084 u32 chavid_ms; /* CHA Version ID Register, MS */
2085 u32 chavid_ls; /* CHA Version ID Register, LS */
2086 u32 chanum_ms; /* CHA Number Register, MS */
2087 u32 chanum_ls; /* CHA Number Register, LS */
2088 u32 secvid_ms; /* SEC Version ID Register, MS */
2089 u32 secvid_ls; /* SEC Version ID Register, LS */
2091 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2092 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2096 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2097 #define SEC_CTPR_MS_QI 0x02000000
2098 #define SEC_RVID_MA 0x0f000000
2099 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2100 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2101 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2102 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2105 typedef struct ccsr_qman {
2107 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2108 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2110 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2113 /* Not actually reserved, but irrelevant to u-boot */
2114 u8 res[0xbf8 - 0x200];
2117 u32 fqd_bare; /* FQD Extended Base Addr Register */
2118 u32 fqd_bar; /* FQD Base Addr Register */
2120 u32 fqd_ar; /* FQD Attributes Register */
2122 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2123 u32 pfdr_bar; /* PFDR Base Addr Register */
2125 u32 pfdr_ar; /* PFDR Attributes Register */
2127 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2128 u32 qcsp_bar; /* QCSP Base Addr Register */
2130 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2131 u32 srcidr; /* Source ID Register */
2132 u32 liodnr; /* LIODN Register */
2134 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2135 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2139 typedef struct ccsr_bman {
2140 /* Not actually reserved, but irrelevant to u-boot */
2144 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2145 u32 fbpr_bar; /* FBPR Base Addr Register */
2147 u32 fbpr_ar; /* FBPR Attributes Register */
2149 u32 srcidr; /* Source ID Register */
2150 u32 liodnr; /* LIODN Register */
2154 typedef struct ccsr_pme {
2156 u32 liodnbr; /* LIODN Base Register */
2158 u32 srcidr; /* Source ID Register */
2160 u32 liodnr; /* LIODN Register */
2162 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2163 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2167 #ifdef CONFIG_FSL_CORENET
2168 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2169 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
2170 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
2171 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2172 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2173 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2174 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2175 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2176 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2177 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2178 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2179 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2180 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2181 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2182 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2183 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2184 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2185 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2186 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2187 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2188 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
2189 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2190 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2191 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2192 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2193 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
2194 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
2195 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2196 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2197 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2198 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2199 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2200 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2201 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2202 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2203 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2204 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2205 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2206 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2207 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2208 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2209 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2211 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2212 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
2213 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2214 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
2215 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2216 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2217 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2218 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2219 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2220 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2221 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2222 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2223 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2225 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2227 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2228 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2229 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2230 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2231 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2232 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
2233 #ifdef CONFIG_TSECV2
2234 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2236 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2238 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2239 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2240 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2241 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2242 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2245 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2246 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2248 #define CONFIG_SYS_FSL_CPC_ADDR \
2249 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2250 #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
2251 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
2252 #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
2253 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
2254 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2255 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2256 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2257 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2258 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2259 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2260 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2261 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2262 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2263 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2264 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
2265 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2266 #define CONFIG_SYS_MPC85xx_DDR_ADDR \
2267 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
2268 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \
2269 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
2270 #define CONFIG_SYS_LBC_ADDR \
2271 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2272 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2273 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2274 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2275 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2276 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2277 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2278 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2279 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2280 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2281 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2282 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2283 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2284 #define CONFIG_SYS_MPC85xx_L2_ADDR \
2285 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2286 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
2287 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2288 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2289 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
2290 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
2291 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
2292 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
2293 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
2294 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
2295 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
2296 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2297 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
2298 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
2299 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
2300 #define CONFIG_SYS_MPC85xx_USB_ADDR \
2301 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
2302 #define CONFIG_SYS_FSL_SEC_ADDR \
2303 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
2304 #define CONFIG_SYS_FSL_FM1_ADDR \
2305 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
2306 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
2307 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
2308 #define CONFIG_SYS_FSL_FM2_ADDR \
2309 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
2311 #define CONFIG_SYS_PCI1_ADDR \
2312 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
2313 #define CONFIG_SYS_PCI2_ADDR \
2314 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
2315 #define CONFIG_SYS_PCIE1_ADDR \
2316 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
2317 #define CONFIG_SYS_PCIE2_ADDR \
2318 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
2319 #define CONFIG_SYS_PCIE3_ADDR \
2320 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
2321 #define CONFIG_SYS_PCIE4_ADDR \
2322 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
2324 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
2325 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
2327 #endif /*__IMMAP_85xx__*/