1 /* originally from linux source.
2 * removed the dependencies on CONFIG_ values
3 * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4 * Modified By Rob Taylor, Flying Pig Systems, 2000
10 #include <asm/byteorder.h>
12 #ifdef CONFIG_ADDR_MAP
16 #define SIO_CONFIG_RA 0x398
17 #define SIO_CONFIG_RD 0x399
23 #define readb(addr) in_8((volatile u8 *)(addr))
24 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
25 #if !defined(__BIG_ENDIAN)
26 #define readw(addr) (*(volatile u16 *) (addr))
27 #define readl(addr) (*(volatile u32 *) (addr))
28 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
29 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
31 #define readw(addr) in_le16((volatile u16 *)(addr))
32 #define readl(addr) in_le32((volatile u32 *)(addr))
33 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
34 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
38 * The insw/outsw/insl/outsl macros don't do byte-swapping.
39 * They are only used in practice for transferring buffers which
40 * are arrays of bytes, and byte-swapping is not appropriate in
43 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
44 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
45 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
46 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
47 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
48 #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
50 #define inb(port) in_8((u8 *)((port)+_IO_BASE))
51 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
52 #if !defined(__BIG_ENDIAN)
53 #define inw(port) in_be16((u16 *)((port)+_IO_BASE))
54 #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
55 #define inl(port) in_be32((u32 *)((port)+_IO_BASE))
56 #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
58 #define inw(port) in_le16((u16 *)((port)+_IO_BASE))
59 #define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
60 #define inl(port) in_le32((u32 *)((port)+_IO_BASE))
61 #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
64 #define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
65 #define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
66 #define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
67 #define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
68 #define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
69 #define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
71 extern void _insb(volatile u8 *port, void *buf, int ns);
72 extern void _outsb(volatile u8 *port, const void *buf, int ns);
73 extern void _insw(volatile u16 *port, void *buf, int ns);
74 extern void _outsw(volatile u16 *port, const void *buf, int ns);
75 extern void _insl(volatile u32 *port, void *buf, int nl);
76 extern void _outsl(volatile u32 *port, const void *buf, int nl);
77 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
78 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
79 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
80 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
83 * The *_ns versions below don't do byte-swapping.
84 * Neither do the standard versions now, these are just here
87 #define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
88 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
89 #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
90 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
93 #define IO_SPACE_LIMIT ~0
95 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
96 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
97 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
100 * Enforce In-order Execution of I/O:
101 * Acts as a barrier to ensure all previous I/O accesses have
102 * completed before any further ones are issued.
104 static inline void eieio(void)
106 __asm__ __volatile__ ("eieio" : : : "memory");
109 static inline void sync(void)
111 __asm__ __volatile__ ("sync" : : : "memory");
114 static inline void isync(void)
116 __asm__ __volatile__ ("isync" : : : "memory");
119 /* Enforce in-order execution of data I/O.
120 * No distinction between read/write on PPC; use eieio for all three.
122 #define iobarrier_rw() eieio()
123 #define iobarrier_r() eieio()
124 #define iobarrier_w() eieio()
127 * Non ordered and non-swapping "raw" accessors
129 #define PCI_FIX_ADDR(addr) (addr)
131 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
133 return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
135 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
137 return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
139 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
141 return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
143 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
145 *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
147 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
149 *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
151 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
153 *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
157 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
159 * Read operations have additional twi & isync to make sure the read
160 * is actually performed (i.e. the data has come back) before we start
161 * executing any following instructions.
163 extern inline u8 in_8(const volatile unsigned char __iomem *addr)
167 __asm__ __volatile__(
168 "sync; lbz%U1%X1 %0,%1;\n"
170 "isync" : "=r" (ret) : "m" (*addr));
174 extern inline void out_8(volatile unsigned char __iomem *addr, u8 val)
176 __asm__ __volatile__("sync;\n"
182 extern inline u16 in_le16(const volatile unsigned short __iomem *addr)
186 __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
188 "isync" : "=r" (ret) :
189 "r" (addr), "m" (*addr));
193 extern inline u16 in_be16(const volatile unsigned short __iomem *addr)
197 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
199 "isync" : "=r" (ret) : "m" (*addr));
203 extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
205 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
206 "r" (val), "r" (addr));
209 extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
211 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
214 extern inline u32 in_le32(const volatile unsigned __iomem *addr)
218 __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
220 "isync" : "=r" (ret) :
221 "r" (addr), "m" (*addr));
225 extern inline u32 in_be32(const volatile unsigned __iomem *addr)
229 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
231 "isync" : "=r" (ret) : "m" (*addr));
235 extern inline void out_le32(volatile unsigned __iomem *addr, u32 val)
237 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
238 "r" (val), "r" (addr));
241 extern inline void out_be32(volatile unsigned __iomem *addr, u32 val)
243 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
246 /* Clear and set bits in one shot. These macros can be used to clear and
247 * set multiple bits in a register using a single call. These macros can
248 * also be used to set a multiple-bit bit pattern using a mask, by
249 * specifying the mask in the 'clear' parameter and the new bit pattern
250 * in the 'set' parameter.
253 #define clrbits(type, addr, clear) \
254 out_##type((addr), in_##type(addr) & ~(clear))
256 #define setbits(type, addr, set) \
257 out_##type((addr), in_##type(addr) | (set))
259 #define clrsetbits(type, addr, clear, set) \
260 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
262 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
263 #define setbits_be32(addr, set) setbits(be32, addr, set)
264 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
266 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
267 #define setbits_le32(addr, set) setbits(le32, addr, set)
268 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
270 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
271 #define setbits_be16(addr, set) setbits(be16, addr, set)
272 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
274 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
275 #define setbits_le16(addr, set) setbits(le16, addr, set)
276 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
278 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
279 #define setbits_8(addr, set) setbits(8, addr, set)
280 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
283 * Given a physical address and a length, return a virtual address
284 * that can be used to access the memory range with the caching
285 * properties specified by "flags".
287 #define MAP_NOCACHE (0)
288 #define MAP_WRCOMBINE (0)
289 #define MAP_WRBACK (0)
290 #define MAP_WRTHROUGH (0)
293 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
295 #ifdef CONFIG_ADDR_MAP
296 return addrmap_phys_to_virt(paddr);
298 return (void *)((unsigned long)paddr);
303 * Take down a mapping set up by map_physmem().
305 static inline void unmap_physmem(void *vaddr, unsigned long flags)
310 static inline phys_addr_t virt_to_phys(void * vaddr)
312 #ifdef CONFIG_ADDR_MAP
313 return addrmap_virt_to_phys(vaddr);
315 return (phys_addr_t)((unsigned long)vaddr);