3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
26 #define CONFIG_NAND_NDFC
28 /* Memory mapped register */
29 #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
34 #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
37 #define SDR0_SDCS0 0x0060
38 #define SDR0_UART0 0x0120 /* UART0 Config */
39 #define SDR0_UART1 0x0121 /* UART1 Config */
40 #define SDR0_SRST 0x0200
41 #define SDR0_CUST0 0x4000
42 #define SDR0_PFC0 0x4100
43 #define SDR0_PFC1 0x4101
44 #define SDR0_MFR 0x4300 /* SDR0_MFR reg */
46 #define SDR0_SDCS_SDD (0x80000000 >> 31)
48 #define SDR0_SRST_DMC (0x80000000 >> 10)
50 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
51 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
52 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
53 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
55 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
56 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
57 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
59 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
60 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
61 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
63 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
64 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
65 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
67 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
68 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
69 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
71 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
72 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
73 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
75 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
76 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
77 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
79 #define SDR0_PFC1_U1ME 0x02000000
80 #define SDR0_PFC1_U0ME 0x00080000
81 #define SDR0_PFC1_U0IM 0x00040000
82 #define SDR0_PFC1_SIS 0x00020000
83 #define SDR0_PFC1_DMAAEN 0x00010000
84 #define SDR0_PFC1_DMADEN 0x00008000
85 #define SDR0_PFC1_USBEN 0x00004000
86 #define SDR0_PFC1_AHBSWAP 0x00000020
87 #define SDR0_PFC1_USBBIGEN 0x00000010
88 #define SDR0_PFC1_GPT_FREQ 0x0000000f
90 #endif /* _PPC405EX_H_ */