1 /*----------------------------------------------------------------------------+
2 | This source code is dual-licensed. You may use it under the terms of the
3 | GNU General Public License version 2, or under the license below.
5 | This source code has been made available to you by IBM on an AS-IS
6 | basis. Anyone receiving this source is licensed under IBM
7 | copyrights to use it in any way he or she deems fit, including
8 | copying it, modifying it, compiling it, and redistributing it either
9 | with or without modifications. No license under IBM patents or
10 | patent applications is to be implied by the copyright license.
12 | Any user of this software should understand that IBM cannot provide
13 | technical support for this software and will not be responsible for
14 | any consequences resulting from the use of this software.
16 | Any person who transfers this source code or any derivative work
17 | must include the IBM copyright notice, this paragraph, and the
18 | preceding two paragraphs in the transferred software.
20 | COPYRIGHT I B M CORPORATION 1999
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 +----------------------------------------------------------------------------*/
26 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
27 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
28 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
29 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
30 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
33 * Stefan Roese, DENX Software Engineering, sr@denx.de.
35 * This program is free software; you can redistribute it and/or
36 * modify it under the terms of the GNU General Public License as
37 * published by the Free Software Foundation; either version 2 of
38 * the License, or (at your option) any later version.
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
54 #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
60 /* Memory mapped registers */
61 #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
62 #define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
63 #define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
64 #define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
68 /* CPR register declarations */
69 #define CPR0_PLLC 0x0040
70 #define CPR0_PLLD 0x0060
71 #define CPR0_PRIMAD0 0x0080
72 #define CPR0_PRIMBD0 0x00a0
73 #define CPR0_OPBD0 0x00c0
74 #define CPR0_PERD 0x00e0
75 #define CPR0_MALD 0x0100
76 #define CPR0_SPCID 0x0120
77 #define CPR0_ICFG 0x0140
79 /* SDR register definations */
80 #define SDR0_SDSTP0 0x0020
81 #define SDR0_SDSTP1 0x0021
82 #define SDR0_PINSTP 0x0040
83 #define SDR0_SDCS0 0x0060
84 #define SDR0_ECID0 0x0080
85 #define SDR0_ECID1 0x0081
86 #define SDR0_ECID2 0x0082
87 #define SDR0_ECID3 0x0083
88 #define SDR0_DDR0 0x00e1
89 #define SDR0_EBC 0x0100
90 #define SDR0_UART0 0x0120
91 #define SDR0_UART1 0x0121
92 #define SDR0_UART2 0x0122
93 #define SDR0_UART3 0x0123
94 #define SDR0_CP440 0x0180
95 #define SDR0_XCR 0x01c0
96 #define SDR0_XCR0 0x01c0
97 #define SDR0_XPLLC 0x01c1
98 #define SDR0_XPLLD 0x01c2
99 #define SDR0_SRST 0x0200
100 #define SDR0_SRST0 SDR0_SRST
101 #define SDR0_SRST1 0x0201
102 #define SDR0_AMP0 0x0240
103 #define SDR0_AMP1 0x0241
104 #define SDR0_USB0 0x0320
105 #define SDR0_CUST0 0x4000
106 #define SDR0_CUST1 0x4002
107 #define SDR0_CUST2 0x4004
108 #define SDR0_CUST3 0x4006
109 #define SDR0_PFC0 0x4100
110 #define SDR0_PFC1 0x4101
111 #define SDR0_PFC2 0x4102
112 #define SDR0_PFC4 0x4104
113 #define SDR0_MFR 0x4300
115 #define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03)
117 #define SDR0_PCI0_PAE_MASK (0x80000000 >> 0)
118 #define SDR0_XCR0_PAE_MASK (0x80000000 >> 0)
120 #define SDR0_PFC0_GEIE_MASK 0x00003e00
121 #define SDR0_PFC0_GEIE_TRE 0x00003e00
122 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
123 #define SDR0_PFC0_TRE_MASK (0x80000000 >> 23)
124 #define SDR0_PFC0_TRE_DISABLE 0x00000000
125 #define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23)
128 * Core Configuration/MMU configuration for 440
130 #define CCR0_DAPUIB 0x00100000
131 #define CCR0_DTB 0x00008000
134 * External Bus Controller
136 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
137 #define PB0CR 0x00 /* periph bank 0 config reg */
138 #define PB1CR 0x01 /* periph bank 1 config reg */
139 #define PB2CR 0x02 /* periph bank 2 config reg */
140 #define PB3CR 0x03 /* periph bank 3 config reg */
141 #define PB4CR 0x04 /* periph bank 4 config reg */
142 #define PB5CR 0x05 /* periph bank 5 config reg */
143 #define PB6CR 0x06 /* periph bank 6 config reg */
144 #define PB7CR 0x07 /* periph bank 7 config reg */
145 #define PB0AP 0x10 /* periph bank 0 access parameters */
146 #define PB1AP 0x11 /* periph bank 1 access parameters */
147 #define PB2AP 0x12 /* periph bank 2 access parameters */
148 #define PB3AP 0x13 /* periph bank 3 access parameters */
149 #define PB4AP 0x14 /* periph bank 4 access parameters */
150 #define PB5AP 0x15 /* periph bank 5 access parameters */
151 #define PB6AP 0x16 /* periph bank 6 access parameters */
152 #define PB7AP 0x17 /* periph bank 7 access parameters */
153 #define PBEAR 0x20 /* periph bus error addr reg */
154 #define PBESR 0x21 /* periph bus error status reg */
155 #define EBC0_CFG 0x23 /* external bus configuration reg */
157 #define SDR0_SDCS_SDD (0x80000000 >> 31)
159 /* todo: move this code from macro offsets to struct */
160 #define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID )
161 #define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID )
162 #define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND )
163 #define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS )
164 #define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID )
165 #define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE)
166 #define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
167 #define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
168 #define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE )
169 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
170 #define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
171 #define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
172 #define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
173 #define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
174 #define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
175 #define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
176 #define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
177 #define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
178 #define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
179 #define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
180 #define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
181 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
182 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
183 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
184 #define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
185 #define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
187 #define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
188 #define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
190 #define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068)
191 #define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c)
192 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
193 #define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074)
194 #define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078)
195 #define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c)
196 #define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080)
197 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
198 #define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088)
199 #define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c)
200 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
202 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
203 #define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c)
204 #define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0)
205 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
206 #define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8)
207 #define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac)
208 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
209 #define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4)
210 #define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8)
212 #define PCIL0_STS (PCIL0_CFGBASE + 0x00e0)
215 * GPIO macro register defines
217 /* todo: move to ppc4xx.h and merge with gpio.h header */
218 #define GPIO0_OR (GPIO0_BASE + 0x0)
219 #define GPIO0_TCR (GPIO0_BASE + 0x4)
220 #define GPIO0_OSRL (GPIO0_BASE + 0x8)
221 #define GPIO0_OSRH (GPIO0_BASE + 0xC)
222 #define GPIO0_TSRL (GPIO0_BASE + 0x10)
223 #define GPIO0_TSRH (GPIO0_BASE + 0x14)
224 #define GPIO0_ODR (GPIO0_BASE + 0x18)
225 #define GPIO0_IR (GPIO0_BASE + 0x1C)
226 #define GPIO0_RR1 (GPIO0_BASE + 0x20)
227 #define GPIO0_RR2 (GPIO0_BASE + 0x24)
228 #define GPIO0_RR3 (GPIO0_BASE + 0x28)
229 #define GPIO0_ISR1L (GPIO0_BASE + 0x30)
230 #define GPIO0_ISR1H (GPIO0_BASE + 0x34)
231 #define GPIO0_ISR2L (GPIO0_BASE + 0x38)
232 #define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
233 #define GPIO0_ISR3L (GPIO0_BASE + 0x40)
234 #define GPIO0_ISR3H (GPIO0_BASE + 0x44)
236 #define GPIO1_OR (GPIO1_BASE + 0x0)
237 #define GPIO1_TCR (GPIO1_BASE + 0x4)
238 #define GPIO1_OSRL (GPIO1_BASE + 0x8)
239 #define GPIO1_OSRH (GPIO1_BASE + 0xC)
240 #define GPIO1_TSRL (GPIO1_BASE + 0x10)
241 #define GPIO1_TSRH (GPIO1_BASE + 0x14)
242 #define GPIO1_ODR (GPIO1_BASE + 0x18)
243 #define GPIO1_IR (GPIO1_BASE + 0x1C)
244 #define GPIO1_RR1 (GPIO1_BASE + 0x20)
245 #define GPIO1_RR2 (GPIO1_BASE + 0x24)
246 #define GPIO1_RR3 (GPIO1_BASE + 0x28)
247 #define GPIO1_ISR1L (GPIO1_BASE + 0x30)
248 #define GPIO1_ISR1H (GPIO1_BASE + 0x34)
249 #define GPIO1_ISR2L (GPIO1_BASE + 0x38)
250 #define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
251 #define GPIO1_ISR3L (GPIO1_BASE + 0x40)
252 #define GPIO1_ISR3H (GPIO1_BASE + 0x44)
254 #endif /* __PPC440_H__ */