git.sur5r.net Git - u-boot/blob - arch/riscv/dts/ae350.dts

   1 /dts-v1/;
   2
   3 / {
   4   #address-cells = <2>;
   5   #size-cells = <2>;
   6   compatible = "andestech,ax25";
   7   model = "andestech,ax25";
   8
   9         aliases {
  10                 uart0 = &serial0;
  11                 spi0 = &spi;
  12         } ;
  13
  14         chosen {
  15                 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
  16                 stdout-path = "uart0:38400n8";
  17   };
  18
  19   cpus {
  20     #address-cells = <1>;
  21     #size-cells = <0>;
  22     timebase-frequency = <10000000>;
  23     CPU0: cpu@0 {
  24       device_type = "cpu";
  25       reg = <0>;
  26       status = "okay";
  27       compatible = "riscv";
  28       riscv,isa = "rv64imafdc";
  29       mmu-type = "riscv,sv39";
  30       clock-frequency = <60000000>;
  31       CPU0_intc: interrupt-controller {
  32         #interrupt-cells = <1>;
  33         interrupt-controller;
  34         compatible = "riscv,cpu-intc";
  35       };
  36     };
  37         };
  38
  39         memory@0 {
  40                 device_type = "memory";
  41     reg = <0x0 0x00000000 0x0 0x40000000>;
  42         };
  43
  44   soc {
  45     #address-cells = <2>;
  46     #size-cells = <2>;
  47     compatible = "andestech,riscv-ae350-soc";
  48     ranges;
  49         };
  50
  51   plmt0@e6000000 {
  52     compatible = "riscv,plmt0";
  53     interrupts-extended = <&CPU0_intc 7>;
  54     reg = <0x0 0xe6000000 0x0 0x100000>;
  55                 };
  56
  57   plic0: interrupt-controller@e4000000 {
  58     compatible = "riscv,plic0";
  59     #address-cells = <2>;
  60     #interrupt-cells = <2>;
  61     interrupt-controller;
  62     reg = <0x0 0xe4000000 0x0 0x2000000>;
  63     riscv,ndev=<31>;
  64     interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
  65         };
  66
  67   plic1: interrupt-controller@e6400000 {
  68     compatible = "riscv,plic1";
  69     #address-cells = <2>;
  70     #interrupt-cells = <2>;
  71                 interrupt-controller;
  72     reg = <0x0 0xe6400000 0x0 0x400000>;
  73     riscv,ndev=<1>;
  74     interrupts-extended = <&CPU0_intc 3>;
  75   };
  76
  77   spiclk: virt_100mhz {
  78     #clock-cells = <0>;
  79     compatible = "fixed-clock";
  80     clock-frequency = <100000000>;
  81   };
  82
  83   timer0: timer@f0400000 {
  84     compatible = "andestech,atcpit100";
  85     reg = <0x0 0xf0400000 0x0 0x1000>;
  86     clock-frequency = <40000000>;
  87     interrupts = <3 4>;
  88     interrupt-parent = <&plic0>;
  89         };
  90
  91         serial0: serial@f0300000 {
  92                 compatible = "andestech,uart16550", "ns16550a";
  93     reg = <0x0 0xf0300000 0x0 0x1000>;
  94     interrupts = <9 4>;
  95                 clock-frequency = <19660800>;
  96                 reg-shift = <2>;
  97                 reg-offset = <32>;
  98                 no-loopback-test = <1>;
  99     interrupt-parent = <&plic0>;
 100         };
 101
 102         mac0: mac@e0100000 {
 103                 compatible = "andestech,atmac100";
 104     reg = <0x0 0xe0100000 0x0 0x1000>;
 105     interrupts = <19 4>;
 106     interrupt-parent = <&plic0>;
 107         };
 108
 109         mmc0: mmc@f0e00000 {
 110     compatible = "andestech,atfsdc010";
 111                 max-frequency = <100000000>;
 112     clock-freq-min-max = <400000 100000000>;
 113                 fifo-depth = <0x10>;
 114     reg = <0x0 0xf0e00000 0x0 0x1000>;
 115     interrupts = <18 4>;
 116                 cap-sd-highspeed;
 117     interrupt-parent = <&plic0>;
 118         };
 119
 120         spi: spi@f0b00000 {
 121                 compatible = "andestech,atcspi200";
 122     reg = <0x0 0xf0b00000 0x0 0x1000>;
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 num-cs = <1>;
 126                 clocks = <&spiclk>;
 127                 interrupts = <3 4>;
 128     interrupt-parent = <&plic0>;
 129                         flash@0 {
 130                         compatible = "spi-flash";
 131                         spi-max-frequency = <50000000>;
 132                         reg = <0>;
 133                         spi-cpol;
 134                         spi-cpha;
 135                 };
 136         };
 137 };