3 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
18 * When handling TLB or caches, we need to do it from P2 area.
20 #define jump_to_P2() \
22 unsigned long __dummy; \
23 __asm__ __volatile__( \
32 : "r" (0x20000000)); \
38 #define back_to_P1() \
40 unsigned long __dummy; \
41 __asm__ __volatile__( \
42 "nop;nop;nop;nop;nop;nop;nop\n\t" \
53 #define CACHE_UPDATED 2
55 static inline void cache_wback_all(void)
57 unsigned long addr, data, i, j;
60 for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
61 for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
62 addr = CACHE_OC_ADDRESS_ARRAY
63 | (j << CACHE_OC_WAY_SHIFT)
64 | (i << CACHE_OC_ENTRY_SHIFT);
66 if (data & CACHE_UPDATED) {
67 data &= ~CACHE_UPDATED;
76 #define CACHE_ENABLE 0
77 #define CACHE_DISABLE 1
79 int cache_control(unsigned int cmd)
86 if (ccr & CCR_CACHE_ENABLE)
89 if (cmd == CACHE_DISABLE)
90 outl(CCR_CACHE_STOP, CCR);
92 outl(CCR_CACHE_INIT, CCR);