1 #ifndef __ASM_SH_CACHE_H
2 #define __ASM_SH_CACHE_H
4 #if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
6 int cache_control(unsigned int cmd);
8 #define L1_CACHE_BYTES 32
10 struct __large_struct { unsigned long buf[100]; };
11 #define __m(x) (*(struct __large_struct *)(x))
13 void dcache_wback_range(u32 start, u32 end);
14 void dcache_invalid_range(u32 start, u32 end);
19 * 32-bytes is the largest L1 data cache line size for SH the architecture. So
20 * it is a safe default for DMA alignment.
22 #define ARCH_DMA_MINALIGN 32
24 #endif /* CONFIG_SH4 || CONFIG_SH4A */
27 * Use the L1 data cache line size value for the minimum DMA buffer alignment
30 #ifndef ARCH_DMA_MINALIGN
31 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
34 #endif /* __ASM_SH_CACHE_H */