2 * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_CPU_SH4_H_
8 #define _ASM_CPU_SH4_H_
11 #define CCR_CACHE_STOP 0x00000808
12 #define CCR_CACHE_ENABLE 0x00000101
13 #define CCR_CACHE_ICI 0x00000800
15 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000
17 #if defined (CONFIG_CPU_SH7750) || \
18 defined(CONFIG_CPU_SH7751)
19 #define CACHE_OC_WAY_SHIFT 14
20 #define CACHE_OC_NUM_ENTRIES 512
22 #define CACHE_OC_WAY_SHIFT 13
23 #define CACHE_OC_NUM_ENTRIES 256
25 #define CACHE_OC_ENTRY_SHIFT 5
27 #if defined (CONFIG_CPU_SH7750) || \
28 defined(CONFIG_CPU_SH7751)
29 # include <asm/cpu_sh7750.h>
30 #elif defined (CONFIG_CPU_SH7722)
31 # include <asm/cpu_sh7722.h>
32 #elif defined (CONFIG_CPU_SH7723)
33 # include <asm/cpu_sh7723.h>
34 #elif defined (CONFIG_CPU_SH7724)
35 # include <asm/cpu_sh7724.h>
36 #elif defined (CONFIG_CPU_SH7734)
37 # include <asm/cpu_sh7734.h>
38 #elif defined (CONFIG_CPU_SH7752)
39 # include <asm/cpu_sh7752.h>
40 #elif defined (CONFIG_CPU_SH7753)
41 # include <asm/cpu_sh7753.h>
42 #elif defined (CONFIG_CPU_SH7757)
43 # include <asm/cpu_sh7757.h>
44 #elif defined (CONFIG_CPU_SH7763)
45 # include <asm/cpu_sh7763.h>
46 #elif defined (CONFIG_CPU_SH7780)
47 # include <asm/cpu_sh7780.h>
48 #elif defined (CONFIG_CPU_SH7785)
49 # include <asm/cpu_sh7785.h>
51 # error "Unknown SH4 variant"
54 #if defined(CONFIG_SH_32BIT)
55 #define PMB_ADDR_ARRAY 0xf6100000
56 #define PMB_ADDR_ENTRY 8
59 #define PMB_DATA_ARRAY 0xf7100000
60 #define PMB_DATA_ENTRY 8
62 #define PMB_UB 9 /* Buffered write */
63 #define PMB_V 8 /* Valid */
64 #define PMB_SZ1 7 /* Page size (upper bit) */
65 #define PMB_SZ0 4 /* Page size (lower bit) */
66 #define PMB_C 3 /* Cacheability */
67 #define PMB_WT 0 /* Write-through */
69 #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
70 #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
71 #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
72 #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
73 ((ppn << PMB_PPN) | (ub << PMB_UB) | \
74 (v << PMB_V) | (sz1 << PMB_SZ1) | \
75 (sz0 << PMB_SZ0) | (c << PMB_C) | \
79 #endif /* _ASM_CPU_SH4_H_ */