2 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 * SH7722 Internal I/O register
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef _ASM_CPU_SH7722_H_
23 #define _ASM_CPU_SH7722_H_
25 #define CACHE_OC_NUM_WAYS 4
26 #define CCR_CACHE_INIT 0x0000090d
29 #define TRA 0xFF000020
30 #define EXPEVT 0xFF000024
31 #define INTEVT 0xFF000028
34 #define PTEH 0xFF000000
35 #define PTEL 0xFF000004
36 #define TTB 0xFF000008
37 #define TEA 0xFF00000C
38 #define MMUCR 0xFF000010
39 #define PASCR 0xFF000070
40 #define IRMCR 0xFF000078
43 #define CCR 0xFF00001C
44 #define RAMCR 0xFF000074
47 #define XSA 0xFF000050
48 #define YSA 0xFF000054
49 #define XDA 0xFF000058
50 #define YDA 0xFF00005C
51 #define XPR 0xFF000060
52 #define YPR 0xFF000064
53 #define XEA 0xFF000068
54 #define YEA 0xFF00006C
57 #define ICR0 0xA4140000
58 #define ICR1 0xA414001C
59 #define INTPRI0 0xA4140010
60 #define INTREQ0 0xA4140024
61 #define INTMSK0 0xA4140044
62 #define INTMSKCLR0 0xA4140064
63 #define NMIFCR 0xA41400C0
64 #define USERIMASK 0xA4700000
65 #define IPRA 0xA4080000
66 #define IPRB 0xA4080004
67 #define IPRC 0xA4080008
68 #define IPRD 0xA408000C
69 #define IPRE 0xA4080010
70 #define IPRF 0xA4080014
71 #define IPRG 0xA4080018
72 #define IPRH 0xA408001C
73 #define IPRI 0xA4080020
74 #define IPRJ 0xA4080024
75 #define IPRK 0xA4080028
76 #define IPRL 0xA408002C
77 #define IMR0 0xA4080080
78 #define IMR1 0xA4080084
79 #define IMR2 0xA4080088
80 #define IMR3 0xA408008C
81 #define IMR4 0xA4080090
82 #define IMR5 0xA4080094
83 #define IMR6 0xA4080098
84 #define IMR7 0xA408009C
85 #define IMR8 0xA40800A0
86 #define IMR9 0xA40800A4
87 #define IMR10 0xA40800A8
88 #define IMR11 0xA40800AC
89 #define IMCR0 0xA40800C0
90 #define IMCR1 0xA40800C4
91 #define IMCR2 0xA40800C8
92 #define IMCR3 0xA40800CC
93 #define IMCR4 0xA40800D0
94 #define IMCR5 0xA40800D4
95 #define IMCR6 0xA40800D8
96 #define IMCR7 0xA40800DC
97 #define IMCR8 0xA40800E0
98 #define IMCR9 0xA40800E4
99 #define IMCR10 0xA40800E8
100 #define IMCR11 0xA40800EC
101 #define MFI_IPRA 0xA40B0000
102 #define MFI_IPRB 0xA40B0004
103 #define MFI_IPRC 0xA40B0008
104 #define MFI_IPRD 0xA40B000C
105 #define MFI_IPRE 0xA40B0010
106 #define MFI_IPRF 0xA40B0014
107 #define MFI_IPRG 0xA40B0018
108 #define MFI_IPRH 0xA40B001C
109 #define MFI_IPRI 0xA40B0020
110 #define MFI_IPRJ 0xA40B0024
111 #define MFI_IPRK 0xA40B0028
112 #define MFI_IPRL 0xA40B002C
113 #define MFI_IMR0 0xA40B0080
114 #define MFI_IMR1 0xA40B0084
115 #define MFI_IMR2 0xA40B0088
116 #define MFI_IMR3 0xA40B008C
117 #define MFI_IMR4 0xA40B0090
118 #define MFI_IMR5 0xA40B0094
119 #define MFI_IMR6 0xA40B0098
120 #define MFI_IMR7 0xA40B009C
121 #define MFI_IMR8 0xA40B00A0
122 #define MFI_IMR9 0xA40B00A4
123 #define MFI_IMR10 0xA40B00A8
124 #define MFI_IMR11 0xA40B00AC
125 #define MFI_IMCR0 0xA40B00C0
126 #define MFI_IMCR1 0xA40B00C4
127 #define MFI_IMCR2 0xA40B00C8
128 #define MFI_IMCR3 0xA40B00CC
129 #define MFI_IMCR4 0xA40B00D0
130 #define MFI_IMCR5 0xA40B00D4
131 #define MFI_IMCR6 0xA40B00D8
132 #define MFI_IMCR7 0xA40B00DC
133 #define MFI_IMCR8 0xA40B00E0
134 #define MFI_IMCR9 0xA40B00E4
135 #define MFI_IMCR10 0xA40B00E8
136 #define MFI_IMCR11 0xA40B00EC
139 #define CMNCR 0xFEC10000
140 #define CS0BCR 0xFEC10004
141 #define CS2BCR 0xFEC10008
142 #define CS4BCR 0xFEC10010
143 #define CS5ABCR 0xFEC10014
144 #define CS5BBCR 0xFEC10018
145 #define CS6ABCR 0xFEC1001C
146 #define CS6BBCR 0xFEC10020
147 #define CS0WCR 0xFEC10024
148 #define CS2WCR 0xFEC10028
149 #define CS4WCR 0xFEC10030
150 #define CS5AWCR 0xFEC10034
151 #define CS5BWCR 0xFEC10038
152 #define CS6AWCR 0xFEC1003C
153 #define CS6BWCR 0xFEC10040
154 #define RBWTCNT 0xFEC10054
157 #define SBSC_SDCR 0xFE400008
158 #define SBSC_SDWCR 0xFE40000C
159 #define SBSC_SDPCR 0xFE400010
160 #define SBSC_RTCSR 0xFE400014
161 #define SBSC_RTCNT 0xFE400018
162 #define SBSC_RTCOR 0xFE40001C
163 #define SBSC_RFCR 0xFE400020
166 #define SAR_0 0xFE008020
167 #define DAR_0 0xFE008024
168 #define TCR_0 0xFE008028
169 #define CHCR_0 0xFE00802C
170 #define SAR_1 0xFE008030
171 #define DAR_1 0xFE008034
172 #define TCR_1 0xFE008038
173 #define CHCR_1 0xFE00803C
174 #define SAR_2 0xFE008040
175 #define DAR_2 0xFE008044
176 #define TCR_2 0xFE008048
177 #define CHCR_2 0xFE00804C
178 #define SAR_3 0xFE008050
179 #define DAR_3 0xFE008054
180 #define TCR_3 0xFE008058
181 #define CHCR_3 0xFE00805C
182 #define SAR_4 0xFE008070
183 #define DAR_4 0xFE008074
184 #define TCR_4 0xFE008078
185 #define CHCR_4 0xFE00807C
186 #define SAR_5 0xFE008080
187 #define DAR_5 0xFE008084
188 #define TCR_5 0xFE008088
189 #define CHCR_5 0xFE00808C
190 #define SARB_0 0xFE008120
191 #define DARB_0 0xFE008124
192 #define TCRB_0 0xFE008128
193 #define SARB_1 0xFE008130
194 #define DARB_1 0xFE008134
195 #define TCRB_1 0xFE008138
196 #define SARB_2 0xFE008140
197 #define DARB_2 0xFE008144
198 #define TCRB_2 0xFE008148
199 #define SARB_3 0xFE008150
200 #define DARB_3 0xFE008154
201 #define TCRB_3 0xFE008158
202 #define DMAOR 0xFE008060
203 #define DMARS_0 0xFE009000
204 #define DMARS_1 0xFE009004
205 #define DMARS_2 0xFE009008
208 #define FRQCR 0xA4150000
209 #define VCLKCR 0xA4150004
210 #define SCLKACR 0xA4150008
211 #define SCLKBCR 0xA415000C
212 #define PLLCR 0xA4150024
213 #define DLLFRQ 0xA4150050
216 #define STBCR 0xA4150020
217 #define MSTPCR0 0xA4150030
218 #define MSTPCR1 0xA4150034
219 #define MSTPCR2 0xA4150038
220 #define BAR 0xA4150040
223 #define RWTCNT 0xA4520000
224 #define RWTCSR 0xA4520004
229 #define TSTR 0xFFD80004
230 #define TCOR0 0xFFD80008
231 #define TCNT0 0xFFD8000C
232 #define TCR0 0xFFD80010
233 #define TCOR1 0xFFD80014
234 #define TCNT1 0xFFD80018
235 #define TCR1 0xFFD8001C
236 #define TCOR2 0xFFD80020
237 #define TCNT2 0xFFD80024
238 #define TCR2 0xFFD80028
241 #define TPU_TSTR 0xA4C90000
242 #define TPU_TCR0 0xA4C90010
243 #define TPU_TMDR0 0xA4C90014
244 #define TPU_TIOR0 0xA4C90018
245 #define TPU_TIER0 0xA4C9001C
246 #define TPU_TSR0 0xA4C90020
247 #define TPU_TCNT0 0xA4C90024
248 #define TPU_TGR0A 0xA4C90028
249 #define TPU_TGR0B 0xA4C9002C
250 #define TPU_TGR0C 0xA4C90030
251 #define TPU_TGR0D 0xA4C90034
252 #define TPU_TCR1 0xA4C90050
253 #define TPU_TMDR1 0xA4C90054
254 #define TPU_TIER1 0xA4C9005C
255 #define TPU_TSR1 0xA4C90060
256 #define TPU_TCNT1 0xA4C90064
257 #define TPU_TGR1A 0xA4C90068
258 #define TPU_TGR1B 0xA4C9006C
259 #define TPU_TGR1C 0xA4C90070
260 #define TPU_TGR1D 0xA4C90074
261 #define TPU_TCR2 0xA4C90090
262 #define TPU_TMDR2 0xA4C90094
263 #define TPU_TIER2 0xA4C9009C
264 #define TPU_TSR2 0xA4C900A0
265 #define TPU_TCNT2 0xA4C900A4
266 #define TPU_TGR2A 0xA4C900A8
267 #define TPU_TGR2B 0xA4C900AC
268 #define TPU_TGR2C 0xA4C900B0
269 #define TPU_TGR2D 0xA4C900B4
270 #define TPU_TCR3 0xA4C900D0
271 #define TPU_TMDR3 0xA4C900D4
272 #define TPU_TIER3 0xA4C900DC
273 #define TPU_TSR3 0xA4C900E0
274 #define TPU_TCNT3 0xA4C900E4
275 #define TPU_TGR3A 0xA4C900E8
276 #define TPU_TGR3B 0xA4C900EC
277 #define TPU_TGR3C 0xA4C900F0
278 #define TPU_TGR3D 0xA4C900F4
281 #define CMSTR 0xA44A0000
282 #define CMCSR 0xA44A0060
283 #define CMCNT 0xA44A0064
284 #define CMCOR 0xA44A0068
287 #define SIOMDR 0xA4500000
288 #define SIOCTR 0xA4500004
289 #define SIOSTBCR0 0xA4500008
290 #define SIOSTBCR1 0xA450000C
291 #define SIOTDR 0xA4500014
292 #define SIORDR 0xA4500018
293 #define SIOSTR 0xA450001C
294 #define SIOIER 0xA4500020
295 #define SIOSCR 0xA4500024
298 #define SIMDR0 0xA4410000
299 #define SISCR0 0xA4410002
300 #define SITDAR0 0xA4410004
301 #define SIRDAR0 0xA4410006
302 #define SICDAR0 0xA4410008
303 #define SICTR0 0xA441000C
304 #define SIFCTR0 0xA4410010
305 #define SISTR0 0xA4410014
306 #define SIIER0 0xA4410016
307 #define SITDR0 0xA4410020
308 #define SIRDR0 0xA4410024
309 #define SITCR0 0xA4410028
310 #define SIRCR0 0xA441002C
311 #define SPICR0 0xA4410030
312 #define SIMDR1 0xA4420000
313 #define SISCR1 0xA4420002
314 #define SITDAR1 0xA4420004
315 #define SIRDAR1 0xA4420006
316 #define SICDAR1 0xA4420008
317 #define SICTR1 0xA442000C
318 #define SIFCTR1 0xA4420010
319 #define SISTR1 0xA4420014
320 #define SIIER1 0xA4420016
321 #define SITDR1 0xA4420020
322 #define SIRDR1 0xA4420024
323 #define SITCR1 0xA4420028
324 #define SIRCR1 0xA442002C
325 #define SPICR1 0xA4420030
328 #define SCIF0_BASE 0xFFE00000
331 #define SIM_SCSMR 0xA4490000
332 #define SIM_SCBRR 0xA4490002
333 #define SIM_SCSCR 0xA4490004
334 #define SIM_SCTDR 0xA4490006
335 #define SIM_SCSSR 0xA4490008
336 #define SIM_SCRDR 0xA449000A
337 #define SIM_SCSCMR 0xA449000C
338 #define SIM_SCSC2R 0xA449000E
339 #define SIM_SCWAIT 0xA4490010
340 #define SIM_SCGRD 0xA4490012
341 #define SIM_SCSMPL 0xA4490014
342 #define SIM_SCDMAEN 0xA4490016
345 #define IRIF_INIT1 0xA45D0012
346 #define IRIF_INIT2 0xA45D0014
347 #define IRIF_RINTCLR 0xA45D0016
348 #define IRIF_TINTCLR 0xA45D0018
349 #define IRIF_SIR0 0xA45D0020
350 #define IRIF_SIR1 0xA45D0022
351 #define IRIF_SIR2 0xA45D0024
352 #define IRIF_SIR3 0xA45D0026
353 #define IRIF_SIR_FRM 0xA45D0028
354 #define IRIF_SIR_EOF 0xA45D002A
355 #define IRIF_SIR_FLG 0xA45D002C
356 #define IRIF_SIR_STS2 0xA45D002E
357 #define IRIF_UART0 0xA45D0030
358 #define IRIF_UART1 0xA45D0032
359 #define IRIF_UART2 0xA45D0034
360 #define IRIF_UART3 0xA45D0036
361 #define IRIF_UART4 0xA45D0038
362 #define IRIF_UART5 0xA45D003A
363 #define IRIF_UART6 0xA45D003C
364 #define IRIF_UART7 0xA45D003E
365 #define IRIF_CRC0 0xA45D0040
366 #define IRIF_CRC1 0xA45D0042
367 #define IRIF_CRC2 0xA45D0044
368 #define IRIF_CRC3 0xA45D0046
369 #define IRIF_CRC4 0xA45D0048
372 #define ICDR0 0xA4470000
373 #define ICCR0 0xA4470004
374 #define ICSR0 0xA4470008
375 #define ICIC0 0xA447000C
376 #define ICCL0 0xA4470010
377 #define ICCH0 0xA4470014
378 #define ICDR1 0xA4750000
379 #define ICCR1 0xA4750004
380 #define ICSR1 0xA4750008
381 #define ICIC1 0xA475000C
382 #define ICCL1 0xA4750010
383 #define ICCH1 0xA4750014
386 #define FLCMNCR 0xA4530000
387 #define FLCMDCR 0xA4530004
388 #define FLCMCDR 0xA4530008
389 #define FLADR 0xA453000C
390 #define FLDATAR 0xA4530010
391 #define FLDTCNTR 0xA4530014
392 #define FLINTDMACR 0xA4530018
393 #define FLBSYTMR 0xA453001C
394 #define FLBSYCNT 0xA4530020
395 #define FLDTFIFO 0xA4530024
396 #define FLECFIFO 0xA4530028
397 #define FLTRCR 0xA453002C
398 #define FLADR2 0xA453003C
401 #define MFIIDX 0xA4C10000
402 #define MFIGSR 0xA4C10004
403 #define MFISCR 0xA4C10008
404 #define MFIMCR 0xA4C1000C
405 #define MFIIICR 0xA4C10010
406 #define MFIEICR 0xA4C10014
407 #define MFIADR 0xA4C10018
408 #define MFIDATA 0xA4C1001C
409 #define MFIRCR 0xA4C10020
410 #define MFIINTEVT 0xA4C1002C
411 #define MFIIMASK 0xA4C10030
412 #define MFIBCR 0xA4C10040
413 #define MFIADRW 0xA4C10044
414 #define MFIADRR 0xA4C10048
415 #define MFIDATAW 0xA4C1004C
416 #define MFIDATAR 0xA4C10050
417 #define MFIMCRW 0xA4C10054
418 #define MFIMCRR 0xA4C10058
419 #define MFIDNRW 0xA4C1005C
420 #define MFIDNRR 0xA4C10060
421 #define MFISIZEW 0xA4C10064
422 #define MFISIZER 0xA4C10068
423 #define MFIDEVCR 0xA4C10038
424 #define MFISM4 0xA4C10080
427 #define VP4_CTRL 0xFE900000
428 #define VP4_VOL_CTRL 0xFE900004
429 #define VP4_IMAGE_SIZE 0xFE900008
430 #define VP4_MB_NUM 0xFE90000C
431 #define VP4_DWY_ADDR 0xFE900010
432 #define VP4_DWC_ADDR 0xFE900014
433 #define VP4_D2WY_ADDR 0xFE900018
434 #define VP4_D2WC_ADDR 0xFE90001C
435 #define VP4_DP1_ADDR 0xFE900020
436 #define VP4_DP2_ADDR 0xFE900024
437 #define VP4_STRS_ADDR 0xFE900028
438 #define VP4_STRE_ADDR 0xFE90002C
439 #define VP4_VOP_CTRL 0xFE900030
440 #define VP4_VOP_TIME 0xFE900034
441 #define VP4_263_CTRL 0xFE900038
442 #define VP4_264_CTRL 0xFE90003C
443 #define VP4_VLC_CTRL 0xFE900040
444 #define VP4_ENDIAN 0xFE900044
445 #define VP4_CMD 0xFE900048
446 #define VP4_ME_TH1 0xFE90004C
447 #define VP4_ME_TH2 0xFE900050
448 #define VP4_ME_COSTMB 0xFE900054
449 #define VP4_ME_SKIP 0xFE900058
450 #define VP4_ME_CTRL 0xFE90005C
451 #define VP4_MBRF_CTRL 0xFE900060
452 #define VP4_MC_CTRL 0xFE900064
453 #define VP4_PRED_CTRL 0xFE900068
454 #define VP4_SLC_SIZE 0xFE90006C
455 #define VP4_VOP_MINBIT 0xFE900070
456 #define VP4_MB_MAXBIT 0xFE900074
457 #define VP4_MB_TBIT 0xFE900078
458 #define VP4_RCQNT 0xFE90007C
459 #define VP4_RCRP 0xFE900080
460 #define VP4_RCDJ 0xFE900084
461 #define VP4_RCWQ 0xFE900088
462 #define VP4_FWD_TIME 0xFE900094
463 #define VP4_BWD_TIME 0xFE900098
464 #define VP4_PST_TIME 0xFE90009C
465 #define VP4_ILTFRAME 0xFE9000A0
466 #define VP4_EC_REF 0xFE9000A4
467 #define VP4_STATUS 0xFE900100
468 #define VP4_IRQ_ENB 0xFE900104
469 #define VP4_IRQ_STA 0xFE900108
470 #define VP4_VOP_BIT 0xFE90010C
471 #define VP4_PRV_BIT 0xFE900110
472 #define VP4_SLC_MB 0xFE900114
473 #define VP4_QSUM 0xFE900118
474 #define VP4_DEC_ERR 0xFE90011C
475 #define VP4_ERR_AREA 0xFE900120
476 #define VP4_NEXT_CODE 0xFE900124
477 #define VP4_MB_ATTR 0xFE900128
478 #define VP4_DBMON 0xFE90012C
479 #define VP4_DEBUG 0xFE900130
480 #define VP4_ERR_DET 0xFE900134
481 #define VP4_CLK_STOP 0xFE900138
482 #define VP4_MB_SADA 0xFE90013C
483 #define VP4_MB_SADR 0xFE900140
484 #define VP4_MAT_RAM 0xFE901000
485 #define VP4_NC_RAM 0xFE902000
486 #define WT 0xFE9020CC
487 #define VP4_CPY_ADDR 0xFE902264
488 #define VP4_CPC_ADDR 0xFE902268
489 #define VP4_R0Y_ADDR 0xFE90226C
490 #define VP4_R0C_ADDR 0xFE902270
491 #define VP4_R1Y_ADDR 0xFE902274
492 #define VP4_R1C_ADDR 0xFE902278
493 #define VP4_R2Y_ADDR 0xFE90227C
494 #define VP4_R2C_ADDR 0xFE902280
495 #define VP4_R3Y_ADDR 0xFE902284
496 #define VP4_R3C_ADDR 0xFE902288
497 #define VP4_R4Y_ADDR 0xFE90228C
498 #define VP4_R4C_ADDR 0xFE902290
499 #define VP4_R5Y_ADDR 0xFE902294
500 #define VP4_R5C_ADDR 0xFE902298
501 #define VP4_R6Y_ADDR 0xFE90229C
502 #define VP4_R6C_ADDR 0xFE9022A0
503 #define VP4_R7Y_ADDR 0xFE9022A4
504 #define VP4_R7C_ADDR 0xFE9022A8
505 #define VP4_R8Y_ADDR 0xFE9022AC
506 #define VP4_R8C_ADDR 0xFE9022B0
507 #define VP4_R9Y_ADDR 0xFE9022B4
508 #define VP4_R9C_ADDR 0xFE9022B8
509 #define VP4_RAY_ADDR 0xFE9022BC
510 #define VP4_RAC_ADDR 0xFE9022C0
511 #define VP4_RBY_ADDR 0xFE9022C4
512 #define VP4_RBC_ADDR 0xFE9022C8
513 #define VP4_RCY_ADDR 0xFE9022CC
514 #define VP4_RCC_ADDR 0xFE9022D0
515 #define VP4_RDY_ADDR 0xFE9022D4
516 #define VP4_RDC_ADDR 0xFE9022D8
517 #define VP4_REY_ADDR 0xFE9022DC
518 #define VP4_REC_ADDR 0xFE9022E0
519 #define VP4_RFY_ADDR 0xFE9022E4
520 #define VP4_RFC_ADDR 0xFE9022E8
523 #define CAPSR 0xFE910000
524 #define CAPCR 0xFE910004
525 #define CAMCR 0xFE910008
526 #define CMCYR 0xFE91000C
527 #define CAMOR 0xFE910010
528 #define CAPWR 0xFE910014
529 #define CAIFR 0xFE910018
530 #define CSTCR 0xFE910020
531 #define CSECR 0xFE910024
532 #define CRCNTR 0xFE910028
533 #define CRCMPR 0xFE91002C
534 #define CFLCR 0xFE910030
535 #define CFSZR 0xFE910034
536 #define CDWDR 0xFE910038
537 #define CDAYR 0xFE91003C
538 #define CDACR 0xFE910040
539 #define CDBYR 0xFE910044
540 #define CDBCR 0xFE910048
541 #define CBDSR 0xFE91004C
542 #define CLFCR 0xFE910060
543 #define CDOCR 0xFE910064
544 #define CDDCR 0xFE910068
545 #define CDDAR 0xFE91006C
546 #define CEIER 0xFE910070
547 #define CETCR 0xFE910074
548 #define CSTSR 0xFE91007C
549 #define CSRTR 0xFE910080
550 #define CDAYR2 0xFE910090
551 #define CDACR2 0xFE910094
552 #define CDBYR2 0xFE910098
553 #define CDBCR2 0xFE91009C
556 #define VESTR 0xFE920000
557 #define VESWR 0xFE920010
558 #define VESSR 0xFE920014
559 #define VSAYR 0xFE920018
560 #define VSACR 0xFE92001C
561 #define VBSSR 0xFE920020
562 #define VEDWR 0xFE920030
563 #define VDAYR 0xFE920034
564 #define VDACR 0xFE920038
565 #define VTRCR 0xFE920050
566 #define VRFCR 0xFE920054
567 #define VRFSR 0xFE920058
568 #define VENHR 0xFE92005C
569 #define VFMCR 0xFE920070
570 #define VVTCR 0xFE920074
571 #define VHTCR 0xFE920078
572 #define VAPCR 0xFE920080
573 #define VECCR 0xFE920084
574 #define VAFXR 0xFE920090
575 #define VSWPR 0xFE920094
576 #define VEIER 0xFE9200A0
577 #define VEVTR 0xFE9200A4
578 #define VSTAR 0xFE9200B0
579 #define VBSRR 0xFE9200B4
582 #define BESTR 0xFE930000
583 #define BSMWR1 0xFE930010
584 #define BSSZR1 0xFE930014
585 #define BSAYR1 0xFE930018
586 #define BSACR1 0xFE93001C
587 #define BSAAR1 0xFE930020
588 #define BSIFR1 0xFE930024
589 #define BSMWR2 0xFE930028
590 #define BSSZR2 0xFE93002C
591 #define BSAYR2 0xFE930030
592 #define BSACR2 0xFE930034
593 #define BSAAR2 0xFE930038
594 #define BSIFR2 0xFE93003C
595 #define BSMWR3 0xFE930040
596 #define BSSZR3 0xFE930044
597 #define BSAYR3 0xFE930048
598 #define BSACR3 0xFE93004C
599 #define BSAAR3 0xFE930050
600 #define BSIFR3 0xFE930054
601 #define BTPSR 0xFE930058
602 #define BMSMWR1 0xFE930070
603 #define BMSSZR1 0xFE930074
604 #define BMSAYR1 0xFE930078
605 #define BMSACR1 0xFE93007C
606 #define BMSMWR2 0xFE930080
607 #define BMSSZR2 0xFE930084
608 #define BMSAYR2 0xFE930088
609 #define BMSACR2 0xFE93008C
610 #define BMSMWR3 0xFE930090
611 #define BMSSZR3 0xFE930094
612 #define BMSAYR3 0xFE930098
613 #define BMSACR3 0xFE93009C
614 #define BMSMWR4 0xFE9300A0
615 #define BMSSZR4 0xFE9300A4
616 #define BMSAYR4 0xFE9300A8
617 #define BMSACR4 0xFE9300AC
618 #define BMSIFR 0xFE9300F0
619 #define BBLCR0 0xFE930100
620 #define BBLCR1 0xFE930104
621 #define BPROCR 0xFE930108
622 #define BMWCR0 0xFE93010C
623 #define BLOCR1 0xFE930114
624 #define BLOCR2 0xFE930118
625 #define BLOCR3 0xFE93011C
626 #define BMLOCR1 0xFE930120
627 #define BMLOCR2 0xFE930124
628 #define BMLOCR3 0xFE930128
629 #define BMLOCR4 0xFE93012C
630 #define BMPCCR1 0xFE930130
631 #define BMPCCR2 0xFE930134
632 #define BPKFR 0xFE930140
633 #define BPCCR0 0xFE930144
634 #define BPCCR11 0xFE930148
635 #define BPCCR12 0xFE93014C
636 #define BPCCR21 0xFE930150
637 #define BPCCR22 0xFE930154
638 #define BPCCR31 0xFE930158
639 #define BPCCR32 0xFE93015C
640 #define BDMWR 0xFE930160
641 #define BDAYR 0xFE930164
642 #define BDACR 0xFE930168
643 #define BAFXR 0xFE930180
644 #define BSWPR 0xFE930184
645 #define BEIER 0xFE930188
646 #define BEVTR 0xFE93018C
647 #define BRCNTR 0xFE930194
648 #define BSTAR 0xFE930198
649 #define BBRSTR 0xFE93019C
650 #define BRCHR 0xFE9301A0
651 #define CLUT 0xFE933000
654 #define JCMOD 0xFEA00000
655 #define JCCMD 0xFEA00004
656 #define JCSTS 0xFEA00008
657 #define JCQTN 0xFEA0000C
658 #define JCHTN 0xFEA00010
659 #define JCDRIU 0xFEA00014
660 #define JCDRID 0xFEA00018
661 #define JCVSZU 0xFEA0001C
662 #define JCVSZD 0xFEA00020
663 #define JCHSZU 0xFEA00024
664 #define JCHSZD 0xFEA00028
665 #define JCDTCU 0xFEA0002C
666 #define JCDTCM 0xFEA00030
667 #define JCDTCD 0xFEA00034
668 #define JINTE 0xFEA00038
669 #define JINTS 0xFEA0003C
670 #define JCDERR 0xFEA00040
671 #define JCRST 0xFEA00044
672 #define JIFCNT 0xFEA00060
673 #define JIFECNT 0xFEA00070
674 #define JIFESYA1 0xFEA00074
675 #define JIFESCA1 0xFEA00078
676 #define JIFESYA2 0xFEA0007C
677 #define JIFESCA2 0xFEA00080
678 #define JIFESMW 0xFEA00084
679 #define JIFESVSZ 0xFEA00088
680 #define JIFESHSZ 0xFEA0008C
681 #define JIFEDA1 0xFEA00090
682 #define JIFEDA2 0xFEA00094
683 #define JIFEDRSZ 0xFEA00098
684 #define JIFDCNT 0xFEA000A0
685 #define JIFDSA1 0xFEA000A4
686 #define JIFDSA2 0xFEA000A8
687 #define JIFDDRSZ 0xFEA000AC
688 #define JIFDDMW 0xFEA000B0
689 #define JIFDDVSZ 0xFEA000B4
690 #define JIFDDHSZ 0xFEA000B8
691 #define JIFDDYA1 0xFEA000BC
692 #define JIFDDCA1 0xFEA000C0
693 #define JIFDDYA2 0xFEA000C4
694 #define JIFDDCA2 0xFEA000C8
695 #define JCQTBL0 0xFEA10000
696 #define JCQTBL1 0xFEA10040
697 #define JCQTBL2 0xFEA10080
698 #define JCQTBL3 0xFEA100C0
699 #define JCHTBD0 0xFEA10100
700 #define JCHTBA0 0xFEA10120
701 #define JCHTBD1 0xFEA10200
702 #define JCHTBA1 0xFEA10220
705 #define MLDDCKPAT1R 0xFE940400
706 #define MLDDCKPAT2R 0xFE940404
707 #define SLDDCKPAT1R 0xFE940408
708 #define SLDDCKPAT2R 0xFE94040C
709 #define LDDCKR 0xFE940410
710 #define LDDCKSTPR 0xFE940414
711 #define MLDMT1R 0xFE940418
712 #define MLDMT2R 0xFE94041C
713 #define MLDMT3R 0xFE940420
714 #define MLDDFR 0xFE940424
715 #define MLDSM1R 0xFE940428
716 #define MLDSM2R 0xFE94042C
717 #define MLDSA1R 0xFE940430
718 #define MLDSA2R 0xFE940434
719 #define MLDMLSR 0xFE940438
720 #define MLDWBFR 0xFE94043C
721 #define MLDWBCNTR 0xFE940440
722 #define MLDWBAR 0xFE940444
723 #define MLDHCNR 0xFE940448
724 #define MLDHSYNR 0xFE94044C
725 #define MLDVLNR 0xFE940450
726 #define MLDVSYNR 0xFE940454
727 #define MLDHPDR 0xFE940458
728 #define MLDVPDR 0xFE94045C
729 #define MLDPMR 0xFE940460
730 #define LDPALCR 0xFE940464
731 #define LDINTR 0xFE940468
732 #define LDSR 0xFE94046C
733 #define LDCNT1R 0xFE940470
734 #define LDCNT2R 0xFE940474
735 #define LDRCNTR 0xFE940478
736 #define LDDDSR 0xFE94047C
737 #define LDRCR 0xFE940484
738 #define LDCMRKRGBR 0xFE9404C4
739 #define LDCMRKCMYR 0xFE9404C8
740 #define LDCMRK1R 0xFE9404CC
741 #define LDCMRK2R 0xFE9404D0
742 #define LDCMGKRGBR 0xFE9404D4
743 #define LDCMGKCMYR 0xFE9404D8
744 #define LDCMGK1R 0xFE9404DC
745 #define LDCMGK2R 0xFE9404E0
746 #define LDCMBKRGBR 0xFE9404E4
747 #define LDCMBKCMYR 0xFE9404E8
748 #define LDCMBK1R 0xFE9404EC
749 #define LDCMBK2R 0xFE9404F0
750 #define LDCMHKPR 0xFE9404F4
751 #define LDCMHKQR 0xFE9404F8
752 #define LDCMSELR 0xFE9404FC
753 #define LDCMTVR 0xFE940500
754 #define LDCMTVSELR 0xFE940504
755 #define LDCMDTHR 0xFE940508
756 #define LDCMCNTR 0xFE94050C
757 #define SLDMT1R 0xFE940600
758 #define SLDMT2R 0xFE940604
759 #define SLDMT3R 0xFE940608
760 #define SLDDFR 0xFE94060C
761 #define SLDSM1R 0xFE940610
762 #define SLDSM2R 0xFE940614
763 #define SLDSA1R 0xFE940618
764 #define SLDSA2R 0xFE94061C
765 #define SLDMLSR 0xFE940620
766 #define SLDHCNR 0xFE940624
767 #define SLDHSYNR 0xFE940628
768 #define SLDVLNR 0xFE94062C
769 #define SLDVSYNR 0xFE940630
770 #define SLDHPDR 0xFE940634
771 #define SLDVPDR 0xFE940638
772 #define SLDPMR 0xFE94063C
773 #define LDDWD0R 0xFE940800
774 #define LDDWD1R 0xFE940804
775 #define LDDWD2R 0xFE940808
776 #define LDDWD3R 0xFE94080C
777 #define LDDWD4R 0xFE940810
778 #define LDDWD5R 0xFE940814
779 #define LDDWD6R 0xFE940818
780 #define LDDWD7R 0xFE94081C
781 #define LDDWD8R 0xFE940820
782 #define LDDWD9R 0xFE940824
783 #define LDDWDAR 0xFE940828
784 #define LDDWDBR 0xFE94082C
785 #define LDDWDCR 0xFE940830
786 #define LDDWDDR 0xFE940834
787 #define LDDWDER 0xFE940838
788 #define LDDWDFR 0xFE94083C
789 #define LDDRDR 0xFE940840
790 #define LDDWAR 0xFE940900
791 #define LDDRAR 0xFE940904
792 #define LDPR00 0xFE940000
795 #define VOUER 0xFE960000
796 #define VOUCR 0xFE960004
797 #define VOUSTR 0xFE960008
798 #define VOUVCR 0xFE96000C
799 #define VOUISR 0xFE960010
800 #define VOUBCR 0xFE960014
801 #define VOUDPR 0xFE960018
802 #define VOUDSR 0xFE96001C
803 #define VOUVPR 0xFE960020
804 #define VOUIR 0xFE960024
805 #define VOUSRR 0xFE960028
806 #define VOUMSR 0xFE96002C
807 #define VOUHIR 0xFE960030
808 #define VOUDFR 0xFE960034
809 #define VOUAD1R 0xFE960038
810 #define VOUAD2R 0xFE96003C
811 #define VOUAIR 0xFE960040
812 #define VOUSWR 0xFE960044
813 #define VOURCR 0xFE960048
814 #define VOURPR 0xFE960050
817 #define TSCTLR 0xA4C80000
818 #define TSPIDR 0xA4C80004
819 #define TSCMDR 0xA4C80008
820 #define TSSTR 0xA4C8000C
821 #define TSTSDR 0xA4C80010
822 #define TSBUFCLRR 0xA4C80014
823 #define TSINTER 0xA4C80018
824 #define TSPSCALER 0xA4C80020
825 #define TSPSCALERR 0xA4C80024
826 #define TSPCRADCMDR 0xA4C80028
827 #define TSPCRADCR 0xA4C8002C
828 #define TSTRPCRADCR 0xA4C80030
829 #define TSDPCRADCR 0xA4C80034
832 #define IFCTL 0xA454C000
833 #define SRCTL 0xA454C004
834 #define SFORM 0xA454C008
835 #define CKCTL 0xA454C00C
836 #define TRDAT 0xA454C010
837 #define STFIFO 0xA454C014
838 #define DPAK 0xA454C01C
839 #define CKREV 0xA454C020
840 #define EVNTC 0xA454C028
841 #define SBCTL 0xA454C040
842 #define SBPSET 0xA454C044
843 #define SBBUS 0xA454C048
844 #define SBWFLG 0xA454C058
845 #define SBRFLG 0xA454C05C
846 #define SBWDAT 0xA454C060
847 #define SBRDAT 0xA454C064
848 #define SBFSTS 0xA454C068
849 #define SBDVCA 0xA454C06C
850 #define SBDVCB 0xA454C070
851 #define SBACTIV 0xA454C074
852 #define DMAIA 0xA454C090
853 #define DMAIB 0xA454C094
854 #define DMAOA 0xA454C098
855 #define DMAOB 0xA454C09C
856 #define SPLRI 0xA454C0B8
857 #define SPRRI 0xA454C0BC
858 #define SPURI 0xA454C0C4
859 #define SPTIS 0xA454C0C8
860 #define SPSTS 0xA454C0CC
861 #define SPCTL 0xA454C0D0
862 #define SPIRI 0xA454C0D4
863 #define SPQCF 0xA454C0D8
864 #define SPQCS 0xA454C0DC
865 #define SPQCT 0xA454C0E0
866 #define DPEAK 0xA454C0F0
867 #define DSLPD 0xA454C0F4
868 #define DSLLV 0xA454C0F8
869 #define BRGASEL 0xA454C100
870 #define BRRA 0xA454C104
871 #define BRGBSEL 0xA454C108
872 #define BRRB 0xA454C10C
875 #define IFR0 0xA4480000
876 #define ISR0 0xA4480010
877 #define IER0 0xA4480020
878 #define EPDR0I 0xA4480030
879 #define EPDR0O 0xA4480034
880 #define EPDR0S 0xA4480038
881 #define EPDR1 0xA448003C
882 #define EPDR2 0xA4480040
883 #define EPDR3 0xA4480044
884 #define EPDR4 0xA4480048
885 #define EPDR5 0xA448004C
886 #define EPDR6 0xA4480050
887 #define EPDR7 0xA4480054
888 #define EPDR8 0xA4480058
889 #define EPDR9 0xA448005C
890 #define EPSZ0O 0xA4480080
891 #define EPSZ3 0xA4480084
892 #define EPSZ6 0xA4480088
893 #define EPSZ9 0xA448008C
894 #define TRG 0xA44800A0
895 #define DASTS 0xA44800A4
896 #define FCLR 0xA44800AA
897 #define DMA 0xA44800AC
898 #define EPSTL 0xA44800B2
899 #define CVR 0xA44800B4
900 #define TSR 0xA44800B8
901 #define CTLR 0xA44800BC
902 #define EPIR 0xA44800C0
903 #define XVERCR 0xA44800D0
904 #define STLMR 0xA44800D4
907 #define KYCR1 0xA44B0000
908 #define KYCR2 0xA44B0004
909 #define KYINDR 0xA44B0008
910 #define KYOUTDR 0xA44B000C
913 #define CMDR0 0xA4448000
914 #define CMDR1 0xA4448001
915 #define CMDR2 0xA4448002
916 #define CMDR3 0xA4448003
917 #define CMDR4 0xA4448004
918 #define CMDR5 0xA4448005
919 #define CMDSTRT 0xA4448006
920 #define OPCR 0xA444800A
921 #define CSTR 0xA444800B
922 #define INTCR0 0xA444800C
923 #define INTCR1 0xA444800D
924 #define INTSTR0 0xA444800E
925 #define INTSTR1 0xA444800F
926 #define CLKON 0xA4448010
927 #define CTOCR 0xA4448011
928 #define VDCNT 0xA4448012
929 #define TBCR 0xA4448014
930 #define MODER 0xA4448016
931 #define CMDTYR 0xA4448018
932 #define RSPTYR 0xA4448019
933 #define TBNCR 0xA444801A
934 #define RSPR0 0xA4448020
935 #define RSPR1 0xA4448021
936 #define RSPR2 0xA4448022
937 #define RSPR3 0xA4448023
938 #define RSPR4 0xA4448024
939 #define RSPR5 0xA4448025
940 #define RSPR6 0xA4448026
941 #define RSPR7 0xA4448027
942 #define RSPR8 0xA4448028
943 #define RSPR9 0xA4448029
944 #define RSPR10 0xA444802A
945 #define RSPR11 0xA444802B
946 #define RSPR12 0xA444802C
947 #define RSPR13 0xA444802D
948 #define RSPR14 0xA444802E
949 #define RSPR15 0xA444802F
950 #define RSPR16 0xA4448030
951 #define RSPRD 0xA4448031
952 #define DTOUTR 0xA4448032
953 #define DR 0xA4448040
954 #define FIFOCLR 0xA4448042
955 #define DMACR 0xA4448044
956 #define INTCR2 0xA4448046
957 #define INTSTR2 0xA4448048
960 #define DLBI 0xFD980000
961 #define DLBD0 0xFD980080
962 #define DLBD1 0xFD980100
963 #define GEWM 0xFD984000
964 #define ICD0 0xFD988000
965 #define ICD1 0xFD989000
966 #define ICT 0xFD98A000
967 #define ILM 0xFD98C000
968 #define FLM0 0xFD98C800
969 #define FLM1 0xFD98D000
970 #define FLUT 0xFD98D800
971 #define Z3D_PC 0xFD98E400
972 #define Z3D_PCSP 0xFD98E404
973 #define Z3D_PAR 0xFD98E408
974 #define Z3D_IMADR 0xFD98E40C
975 #define Z3D_BTR0 0xFD98E410
976 #define Z3D_BTR1 0xFD98E414
977 #define Z3D_BTR2 0xFD98E418
978 #define Z3D_BTR3 0xFD98E41C
979 #define Z3D_LC0 0xFD98E420
980 #define Z3D_LC1 0xFD98E424
981 #define Z3D_LC2 0xFD98E428
982 #define Z3D_LC3 0xFD98E42C
983 #define Z3D_FR0 0xFD98E430
984 #define Z3D_FR1 0xFD98E434
985 #define Z3D_FR2 0xFD98E438
986 #define Z3D_SR 0xFD98E440
987 #define Z3D_SMDR 0xFD98E444
988 #define Z3D_PBIR 0xFD98E448
989 #define Z3D_DMDR 0xFD98E44C
990 #define Z3D_IREG 0xFD98E460
991 #define Z3D_AR00 0xFD98E480
992 #define Z3D_AR01 0xFD98E484
993 #define Z3D_AR02 0xFD98E488
994 #define Z3D_AR03 0xFD98E48C
995 #define Z3D_BR00 0xFD98E490
996 #define Z3D_BR01 0xFD98E494
997 #define Z3D_IXR00 0xFD98E4A0
998 #define Z3D_IXR01 0xFD98E4A4
999 #define Z3D_IXR02 0xFD98E4A8
1000 #define Z3D_IXR03 0xFD98E4AC
1001 #define Z3D_AR10 0xFD98E4C0
1002 #define Z3D_AR11 0xFD98E4C4
1003 #define Z3D_AR12 0xFD98E4C8
1004 #define Z3D_AR13 0xFD98E4CC
1005 #define Z3D_BR10 0xFD98E4D0
1006 #define Z3D_BR11 0xFD98E4D4
1007 #define Z3D_IXR10 0xFD98E4E0
1008 #define Z3D_IXR11 0xFD98E4E4
1009 #define Z3D_IXR12 0xFD98E4E8
1010 #define Z3D_IXR13 0xFD98E4EC
1011 #define Z3D_AR20 0xFD98E500
1012 #define Z3D_AR21 0xFD98E504
1013 #define Z3D_AR22 0xFD98E508
1014 #define Z3D_AR23 0xFD98E50C
1015 #define Z3D_BR20 0xFD98E510
1016 #define Z3D_BR21 0xFD98E514
1017 #define Z3D_IXR20 0xFD98E520
1018 #define Z3D_IXR21 0xFD98E524
1019 #define Z3D_IXR22 0xFD98E528
1020 #define Z3D_IXR23 0xFD98E52C
1021 #define Z3D_MR0 0xFD98E540
1022 #define Z3D_MR1 0xFD98E544
1023 #define Z3D_MR2 0xFD98E548
1024 #define Z3D_MR3 0xFD98E54C
1025 #define Z3D_WORKRST 0xFD98E558
1026 #define Z3D_WORKWST 0xFD98E55C
1027 #define Z3D_DBADR 0xFD98E560
1028 #define Z3D_DLBPRST 0xFD98E564
1029 #define Z3D_DLBRST 0xFD98E568
1030 #define Z3D_DLBWST 0xFD98E56C
1031 #define Z3D_UDR0 0xFD98E570
1032 #define Z3D_UDR1 0xFD98E574
1033 #define Z3D_UDR2 0xFD98E578
1034 #define Z3D_UDR3 0xFD98E57C
1035 #define Z3D_CCR0 0xFD98E580
1036 #define Z3D_CCR1 0xFD98E584
1037 #define Z3D_EXPR 0xFD98E588
1038 #define Z3D_V0_X 0xFD9A0000
1039 #define Z3D_V0_Y 0xFD9A0004
1040 #define Z3D_V0_Z 0xFD9A0008
1041 #define Z3D_V0_W 0xFD9A000C
1042 #define Z3D_V0_A 0xFD9A0010
1043 #define Z3D_V0_R 0xFD9A0014
1044 #define Z3D_V0_G 0xFD9A0018
1045 #define Z3D_V0_B 0xFD9A001C
1046 #define Z3D_V0_F 0xFD9A0020
1047 #define Z3D_V0_SR 0xFD9A0024
1048 #define Z3D_V0_SG 0xFD9A0028
1049 #define Z3D_V0_SB 0xFD9A002C
1050 #define Z3D_V0_U0 0xFD9A0030
1051 #define Z3D_V0_V0 0xFD9A0034
1052 #define Z3D_V0_U1 0xFD9A0038
1053 #define Z3D_V0_V1 0xFD9A003C
1054 #define Z3D_V1_X 0xFD9A0080
1055 #define Z3D_V1_Y 0xFD9A0084
1056 #define Z3D_V1_Z 0xFD9A0088
1057 #define Z3D_V1_W 0xFD9A008C
1058 #define Z3D_V1_A 0xFD9A0090
1059 #define Z3D_V1_R 0xFD9A0094
1060 #define Z3D_V1_G 0xFD9A0098
1061 #define Z3D_V1_B 0xFD9A009C
1062 #define Z3D_V1_F 0xFD9A00A0
1063 #define Z3D_V1_SR 0xFD9A00A4
1064 #define Z3D_V1_SG 0xFD9A00A8
1065 #define Z3D_V1_SB 0xFD9A00AC
1066 #define Z3D_V1_U0 0xFD9A00B0
1067 #define Z3D_V1_V0 0xFD9A00B4
1068 #define Z3D_V1_U1 0xFD9A00B8
1069 #define Z3D_V1_V1 0xFD9A00BC
1070 #define Z3D_V2_X 0xFD9A0100
1071 #define Z3D_V2_Y 0xFD9A0104
1072 #define Z3D_V2_Z 0xFD9A0108
1073 #define Z3D_V2_W 0xFD9A010C
1074 #define Z3D_V2_A 0xFD9A0110
1075 #define Z3D_V2_R 0xFD9A0114
1076 #define Z3D_V2_G 0xFD9A0118
1077 #define Z3D_V2_B 0xFD9A011C
1078 #define Z3D_V2_F 0xFD9A0120
1079 #define Z3D_V2_SR 0xFD9A0124
1080 #define Z3D_V2_SG 0xFD9A0128
1081 #define Z3D_V2_SB 0xFD9A012C
1082 #define Z3D_V2_U0 0xFD9A0130
1083 #define Z3D_V2_V0 0xFD9A0134
1084 #define Z3D_V2_U1 0xFD9A0138
1085 #define Z3D_V2_V1 0xFD9A013C
1086 #define Z3D_RENDER 0xFD9A0180
1087 #define Z3D_POLYGON_OFFSET 0xFD9A0184
1088 #define Z3D_VERTEX_CONTROL 0xFD9A0200
1089 #define Z3D_STATE_MODE 0xFD9A0204
1090 #define Z3D_FPU_MODE 0xFD9A0318
1091 #define Z3D_SCISSOR_MIN 0xFD9A0400
1092 #define Z3D_SCISSOR_MAX 0xFD9A0404
1093 #define Z3D_TEXTURE_MODE_A 0xFD9A0408
1094 #define Z3D_TEXTURE_MODE_B 0xFD9A040C
1095 #define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418
1096 #define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C
1097 #define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420
1098 #define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424
1099 #define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438
1100 #define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C
1101 #define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440
1102 #define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444
1103 #define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448
1104 #define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C
1105 #define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450
1106 #define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454
1107 #define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458
1108 #define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C
1109 #define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460
1110 #define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464
1111 #define Z3D_TEXTURE_FLUSH 0xFD9A0498
1112 #define Z3D_GAMMA_TABLE0 0xFD9A049C
1113 #define Z3D_GAMMA_TABLE1 0xFD9A04A0
1114 #define Z3D_GAMMA_TABLE2 0xFD9A04A4
1115 #define Z3D_ALPHA_TEST 0xFD9A0800
1116 #define Z3D_STENCIL_TEST 0xFD9A0804
1117 #define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808
1118 #define Z3D_MASK 0xFD9A080C
1119 #define Z3D_FBUS_MODE 0xFD9A0810
1120 #define Z3D_GNT_SET 0xFD9A0814
1121 #define Z3D_BETWEEN_TEST 0xFD9A0818
1122 #define Z3D_FB_BASE 0xFD9A081C
1123 #define Z3D_LCD_SIZE 0xFD9A0820
1124 #define Z3D_FB_FLUSH 0xFD9A0824
1125 #define Z3D_CACHE_INVALID 0xFD9A0828
1126 #define Z3D_SC_MODE 0xFD9A0830
1127 #define Z3D_SC0_MIN 0xFD9A0834
1128 #define Z3D_SC0_MAX 0xFD9A0838
1129 #define Z3D_SC1_MIN 0xFD9A083C
1130 #define Z3D_SC1_MAX 0xFD9A0840
1131 #define Z3D_SC2_MIN 0xFD9A0844
1132 #define Z3D_SC2_MAX 0xFD9A0848
1133 #define Z3D_SC3_MIN 0xFD9A084C
1134 #define Z3D_SC3_MAX 0xFD9A0850
1135 #define Z3D_READRESET 0xFD9A0854
1136 #define Z3D_DET_MIN 0xFD9A0858
1137 #define Z3D_DET_MAX 0xFD9A085C
1138 #define Z3D_FB_BASE_SR 0xFD9A0860
1139 #define Z3D_LCD_SIZE_SR 0xFD9A0864
1140 #define Z3D_2D_CTRL_STATUS 0xFD9A0C00
1141 #define Z3D_2D_SIZE 0xFD9A0C04
1142 #define Z3D_2D_SRCLOC 0xFD9A0C08
1143 #define Z3D_2D_DSTLOC 0xFD9A0C0C
1144 #define Z3D_2D_DMAPORT 0xFD9A0C10
1145 #define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14
1146 #define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18
1147 #define Z3D_2D_STPCOLOR0 0xFD9A0C1C
1148 #define Z3D_2D_STPCOLOR1 0xFD9A0C20
1149 #define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24
1150 #define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28
1151 #define Z3D_2D_STPPAT_0 0xFD9A0C40
1152 #define Z3D_2D_STPPAT_1 0xFD9A0C44
1153 #define Z3D_2D_STPPAT_2 0xFD9A0C48
1154 #define Z3D_2D_STPPAT_3 0xFD9A0C4C
1155 #define Z3D_2D_STPPAT_4 0xFD9A0C50
1156 #define Z3D_2D_STPPAT_5 0xFD9A0C54
1157 #define Z3D_2D_STPPAT_6 0xFD9A0C58
1158 #define Z3D_2D_STPPAT_7 0xFD9A0C5C
1159 #define Z3D_2D_STPPAT_8 0xFD9A0C60
1160 #define Z3D_2D_STPPAT_9 0xFD9A0C64
1161 #define Z3D_2D_STPPAT_10 0xFD9A0C68
1162 #define Z3D_2D_STPPAT_11 0xFD9A0C6C
1163 #define Z3D_2D_STPPAT_12 0xFD9A0C70
1164 #define Z3D_2D_STPPAT_13 0xFD9A0C74
1165 #define Z3D_2D_STPPAT_14 0xFD9A0C78
1166 #define Z3D_2D_STPPAT_15 0xFD9A0C7C
1167 #define Z3D_2D_STPPAT_16 0xFD9A0C80
1168 #define Z3D_2D_STPPAT_17 0xFD9A0C84
1169 #define Z3D_2D_STPPAT_18 0xFD9A0C88
1170 #define Z3D_2D_STPPAT_19 0xFD9A0C8C
1171 #define Z3D_2D_STPPAT_20 0xFD9A0C90
1172 #define Z3D_2D_STPPAT_21 0xFD9A0C94
1173 #define Z3D_2D_STPPAT_22 0xFD9A0C98
1174 #define Z3D_2D_STPPAT_23 0xFD9A0C9C
1175 #define Z3D_2D_STPPAT_24 0xFD9A0CA0
1176 #define Z3D_2D_STPPAT_25 0xFD9A0CA4
1177 #define Z3D_2D_STPPAT_26 0xFD9A0CA8
1178 #define Z3D_2D_STPPAT_27 0xFD9A0CAC
1179 #define Z3D_2D_STPPAT_28 0xFD9A0CB0
1180 #define Z3D_2D_STPPAT_29 0xFD9A0CB4
1181 #define Z3D_2D_STPPAT_30 0xFD9A0CB8
1182 #define Z3D_2D_STPPAT_31 0xFD9A0CBC
1183 #define Z3D_WR_CTRL 0xFD9A1000
1184 #define Z3D_WR_P0 0xFD9A1004
1185 #define Z3D_WR_P1 0xFD9A1008
1186 #define Z3D_WR_P2 0xFD9A100C
1187 #define Z3D_WR_FGC 0xFD9A1010
1188 #define Z3D_WR_BGC 0xFD9A1014
1189 #define Z3D_WR_SZ 0xFD9A1018
1190 #define Z3D_WR_PATPARAM 0xFD9A101C
1191 #define Z3D_WR_PAT 0xFD9A1020
1192 #define Z3D_SYS_STATUS 0xFD9A1400
1193 #define Z3D_SYS_RESET 0xFD9A1404
1194 #define Z3D_SYS_CLK 0xFD9A1408
1195 #define Z3D_SYS_CONF 0xFD9A140C
1196 #define Z3D_SYS_VERSION 0xFD9A1410
1197 #define Z3D_SYS_DBINV 0xFD9A1418
1198 #define Z3D_SYS_I2F_FMT 0xFD9A1420
1199 #define Z3D_SYS_I2F_SRC 0xFD9A1424
1200 #define Z3D_SYS_I2F_DST 0xFD9A1428
1201 #define Z3D_SYS_GBCNT 0xFD9A1430
1202 #define Z3D_SYS_BSYCNT 0xFD9A1434
1203 #define Z3D_SYS_INT_STATUS 0xFD9A1450
1204 #define Z3D_SYS_INT_MASK 0xFD9A1454
1205 #define Z3D_SYS_INT_CLEAR 0xFD9A1458
1206 #define TCD0 0xFD9C0000
1207 #define TCD1 0xFD9C0400
1208 #define TCD2 0xFD9C0800
1209 #define TCD3 0xFD9C0C00
1210 #define TCT0 0xFD9C1000
1211 #define TCT1 0xFD9C1400
1212 #define TCT2 0xFD9C1800
1213 #define TCT3 0xFD9C1C00
1216 #define PACR 0xA4050100
1217 #define PBCR 0xA4050102
1218 #define PCCR 0xA4050104
1219 #define PDCR 0xA4050106
1220 #define PECR 0xA4050108
1221 #define PFCR 0xA405010A
1222 #define PGCR 0xA405010C
1223 #define PHCR 0xA405010E
1224 #define PJCR 0xA4050110
1225 #define PKCR 0xA4050112
1226 #define PLCR 0xA4050114
1227 #define PMCR 0xA4050116
1228 #define PNCR 0xA4050118
1229 #define PQCR 0xA405011A
1230 #define PRCR 0xA405011C
1231 #define PSCR 0xA405011E
1232 #define PTCR 0xA4050140
1233 #define PUCR 0xA4050142
1234 #define PVCR 0xA4050144
1235 #define PWCR 0xA4050146
1236 #define PXCR 0xA4050148
1237 #define PYCR 0xA405014A
1238 #define PZCR 0xA405014C
1239 #define PSELA 0xA405014E
1240 #define PSELB 0xA4050150
1241 #define PSELC 0xA4050152
1242 #define PSELD 0xA4050154
1243 #define PSELE 0xA4050156
1244 #define HIZCRA 0xA4050158
1245 #define HIZCRB 0xA405015A
1246 #define HIZCRC 0xA405015C
1247 #define HIZCRC 0xA405015C
1248 #define MSELCRA 0xA4050180
1249 #define MSELCRB 0xA4050182
1250 #define PULCR 0xA4050184
1251 #define SBSCR 0xA4050186
1252 #define DRVCR 0xA405018A
1255 #define PADR 0xA4050120
1256 #define PBDR 0xA4050122
1257 #define PCDR 0xA4050124
1258 #define PDDR 0xA4050126
1259 #define PEDR 0xA4050128
1260 #define PFDR 0xA405012A
1261 #define PGDR 0xA405012C
1262 #define PHDR 0xA405012E
1263 #define PJDR 0xA4050130
1264 #define PKDR 0xA4050132
1265 #define PLDR 0xA4050134
1266 #define PMDR 0xA4050136
1267 #define PNDR 0xA4050138
1268 #define PQDR 0xA405013A
1269 #define PRDR 0xA405013C
1270 #define PSDR 0xA405013E
1271 #define PTDR 0xA4050160
1272 #define PUDR 0xA4050162
1273 #define PVDR 0xA4050164
1274 #define PWDR 0xA4050166
1275 #define PYDR 0xA4050168
1276 #define PZDR 0xA405016A
1279 #define CBR0 0xFF200000
1280 #define CRR0 0xFF200004
1281 #define CAR0 0xFF200008
1282 #define CAMR0 0xFF20000C
1283 #define CBR1 0xFF200020
1284 #define CRR1 0xFF200024
1285 #define CAR1 0xFF200028
1286 #define CAMR1 0xFF20002C
1287 #define CDR1 0xFF200030
1288 #define CDMR1 0xFF200034
1289 #define CETR1 0xFF200038
1290 #define CCMFR 0xFF200600
1291 #define CBCR 0xFF200620
1294 #define SDIR 0xFC110000
1295 #define SDDRH 0xFC110008
1296 #define SDDRL 0xFC11000A
1297 #define SDINT 0xFC110018
1299 #endif /* _ASM_CPU_SH7722_H_ */