1 #ifndef _ASM_CPU_SH7780_H_
2 #define _ASM_CPU_SH7780_H_
5 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
6 * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 #define CACHE_OC_NUM_WAYS 1
12 #define CCR_CACHE_INIT 0x0000090b
15 #define TRA 0xFF000020
16 #define EXPEVT 0xFF000024
17 #define INTEVT 0xFF000028
19 /* Memory Management Unit */
20 #define PTEH 0xFF000000
21 #define PTEL 0xFF000004
22 #define TTB 0xFF000008
23 #define TEA 0xFF00000C
24 #define MMUCR 0xFF000010
25 #define PASCR 0xFF000070
26 #define IRMCR 0xFF000078
28 /* Cache Controller */
29 #define CCR 0xFF00001C
30 #define QACR0 0xFF000038
31 #define QACR1 0xFF00003C
32 #define RAMCR 0xFF000074
35 #define RAMCR 0xFF000074
36 #define LSA0 0xFF000050
37 #define LSA1 0xFF000054
38 #define LDA0 0xFF000058
39 #define LDA1 0xFF00005C
41 /* Interrupt Controller */
42 #define ICR0 0xFFD00000
43 #define ICR1 0xFFD0001C
44 #define INTPRI 0xFFD00010
45 #define INTREQ 0xFFD00024
46 #define INTMSK0 0xFFD00044
47 #define INTMSK1 0xFFD00048
48 #define INTMSK2 0xFFD40080
49 #define INTMSKCLR0 0xFFD00064
50 #define INTMSKCLR1 0xFFD00068
51 #define INTMSKCLR2 0xFFD40084
52 #define NMIFCR 0xFFD000C0
53 #define USERIMASK 0xFFD30000
54 #define INT2PRI0 0xFFD40000
55 #define INT2PRI1 0xFFD40004
56 #define INT2PRI2 0xFFD40008
57 #define INT2PRI3 0xFFD4000C
58 #define INT2PRI4 0xFFD40010
59 #define INT2PRI5 0xFFD40014
60 #define INT2PRI6 0xFFD40018
61 #define INT2PRI7 0xFFD4001C
62 #define INT2A0 0xFFD40030
63 #define INT2A1 0xFFD40034
64 #define INT2MSKR 0xFFD40038
65 #define INT2MSKCR 0xFFD4003C
66 #define INT2B0 0xFFD40040
67 #define INT2B1 0xFFD40044
68 #define INT2B2 0xFFD40048
69 #define INT2B3 0xFFD4004C
70 #define INT2B4 0xFFD40050
71 #define INT2B5 0xFFD40054
72 #define INT2B6 0xFFD40058
73 #define INT2B7 0xFFD4005C
74 #define INT2GPIC 0xFFD40090
76 /* local Bus State Controller */
77 #define MMSELR 0xFF400020
78 #define BCR 0xFF801000
79 #define CS0BCR 0xFF802000
80 #define CS1BCR 0xFF802010
81 #define CS2BCR 0xFF802020
82 #define CS4BCR 0xFF802040
83 #define CS5BCR 0xFF802050
84 #define CS6BCR 0xFF802060
85 #define CS0WCR 0xFF802008
86 #define CS1WCR 0xFF802018
87 #define CS2WCR 0xFF802028
88 #define CS4WCR 0xFF802048
89 #define CS5WCR 0xFF802058
90 #define CS6WCR 0xFF802068
91 #define CS5PCR 0xFF802070
92 #define CS6PCR 0xFF802080
95 #define MIM_1 0xFE800008
96 #define MIM_2 0xFE80000C
97 #define SCR_1 0xFE800010
98 #define SCR_2 0xFE800014
99 #define STR_1 0xFE800018
100 #define STR_2 0xFE80001C
101 #define SDR_1 0xFE800030
102 #define SDR_2 0xFE800034
103 #define DBK_1 0xFE800400
104 #define DBK_2 0xFE800404
107 #define SH7780_PCIECR 0xFE000008
108 #define SH7780_PCIVID 0xFE040000
109 #define SH7780_PCIDID 0xFE040002
110 #define SH7780_PCICMD 0xFE040004
111 #define SH7780_PCISTATUS 0xFE040006
112 #define SH7780_PCIRID 0xFE040008
113 #define SH7780_PCIPIF 0xFE040009
114 #define SH7780_PCISUB 0xFE04000A
115 #define SH7780_PCIBCC 0xFE04000B
116 #define SH7780_PCICLS 0xFE04000C
117 #define SH7780_PCILTM 0xFE04000D
118 #define SH7780_PCIHDR 0xFE04000E
119 #define SH7780_PCIBIST 0xFE04000F
120 #define SH7780_PCIIBAR 0xFE040010
121 #define SH7780_PCIMBAR0 0xFE040014
122 #define SH7780_PCIMBAR1 0xFE040018
123 #define SH7780_PCISVID 0xFE04002C
124 #define SH7780_PCISID 0xFE04002E
125 #define SH7780_PCICP 0xFE040034
126 #define SH7780_PCIINTLINE 0xFE04003C
127 #define SH7780_PCIINTPIN 0xFE04003D
128 #define SH7780_PCIMINGNT 0xFE04003E
129 #define SH7780_PCIMAXLAT 0xFE04003F
130 #define SH7780_PCICID 0xFE040040
131 #define SH7780_PCINIP 0xFE040041
132 #define SH7780_PCIPMC 0xFE040042
133 #define SH7780_PCIPMCSR 0xFE040044
134 #define SH7780_PCIPMCSRBSE 0xFE040046
135 #define SH7780_PCI_CDD 0xFE040047
136 #define SH7780_PCICR 0xFE040100
137 #define SH7780_PCILSR0 0xFE040104
138 #define SH7780_PCILSR1 0xFE040108
139 #define SH7780_PCILAR0 0xFE04010C
140 #define SH7780_PCILAR1 0xFE040110
141 #define SH7780_PCIIR 0xFE040114
142 #define SH7780_PCIIMR 0xFE040118
143 #define SH7780_PCIAIR 0xFE04011C
144 #define SH7780_PCICIR 0xFE040120
145 #define SH7780_PCIAINT 0xFE040130
146 #define SH7780_PCIAINTM 0xFE040134
147 #define SH7780_PCIBMIR 0xFE040138
148 #define SH7780_PCIPAR 0xFE0401C0
149 #define SH7780_PCIPINT 0xFE0401CC
150 #define SH7780_PCIPINTM 0xFE0401D0
151 #define SH7780_PCIMBR0 0xFE0401E0
152 #define SH7780_PCIMBMR0 0xFE0401E4
153 #define SH7780_PCIMBR1 0xFE0401E8
154 #define SH7780_PCIMBMR1 0xFE0401EC
155 #define SH7780_PCIMBR2 0xFE0401F0
156 #define SH7780_PCIMBMR2 0xFE0401F4
157 #define SH7780_PCIIOBR 0xFE0401F8
158 #define SH7780_PCIIOBMR 0xFE0401FC
159 #define SH7780_PCICSCR0 0xFE040210
160 #define SH7780_PCICSCR1 0xFE040214
161 #define SH7780_PCICSAR0 0xFE040218
162 #define SH7780_PCICSAR1 0xFE04021C
163 #define SH7780_PCIPDR 0xFE040220
166 #define DMAC_SAR0 0xFC808020
167 #define DMAC_DAR0 0xFC808024
168 #define DMAC_TCR0 0xFC808028
169 #define DMAC_CHCR0 0xFC80802C
170 #define DMAC_SAR1 0xFC808030
171 #define DMAC_DAR1 0xFC808034
172 #define DMAC_TCR1 0xFC808038
173 #define DMAC_CHCR1 0xFC80803C
174 #define DMAC_SAR2 0xFC808040
175 #define DMAC_DAR2 0xFC808044
176 #define DMAC_TCR2 0xFC808048
177 #define DMAC_CHCR2 0xFC80804C
178 #define DMAC_SAR3 0xFC808050
179 #define DMAC_DAR3 0xFC808054
180 #define DMAC_TCR3 0xFC808058
181 #define DMAC_CHCR3 0xFC80805C
182 #define DMAC_DMAOR0 0xFC808060
183 #define DMAC_SAR4 0xFC808070
184 #define DMAC_DAR4 0xFC808074
185 #define DMAC_TCR4 0xFC808078
186 #define DMAC_CHCR4 0xFC80807C
187 #define DMAC_SAR5 0xFC808080
188 #define DMAC_DAR5 0xFC808084
189 #define DMAC_TCR5 0xFC808088
190 #define DMAC_CHCR5 0xFC80808C
191 #define DMAC_SARB0 0xFC808120
192 #define DMAC_DARB0 0xFC808124
193 #define DMAC_TCRB0 0xFC808128
194 #define DMAC_SARB1 0xFC808130
195 #define DMAC_DARB1 0xFC808134
196 #define DMAC_TCRB1 0xFC808138
197 #define DMAC_SARB2 0xFC808140
198 #define DMAC_DARB2 0xFC808144
199 #define DMAC_TCRB2 0xFC808148
200 #define DMAC_SARB3 0xFC808150
201 #define DMAC_DARB3 0xFC808154
202 #define DMAC_TCRB3 0xFC808158
203 #define DMAC_DMARS0 0xFC809000
204 #define DMAC_DMARS1 0xFC809004
205 #define DMAC_DMARS2 0xFC809008
206 #define DMAC_SAR6 0xFC818020
207 #define DMAC_DAR6 0xFC818024
208 #define DMAC_TCR6 0xFC818028
209 #define DMAC_CHCR6 0xFC81802C
210 #define DMAC_SAR7 0xFC818030
211 #define DMAC_DAR7 0xFC818034
212 #define DMAC_TCR7 0xFC818038
213 #define DMAC_CHCR7 0xFC81803C
214 #define DMAC_SAR8 0xFC818040
215 #define DMAC_DAR8 0xFC818044
216 #define DMAC_TCR8 0xFC818048
217 #define DMAC_CHCR8 0xFC81804C
218 #define DMAC_SAR9 0xFC818050
219 #define DMAC_DAR9 0xFC818054
220 #define DMAC_TCR9 0xFC818058
221 #define DMAC_CHCR9 0xFC81805C
222 #define DMAC_DMAOR1 0xFC818060
223 #define DMAC_SAR10 0xFC818070
224 #define DMAC_DAR10 0xFC818074
225 #define DMAC_TCR10 0xFC818078
226 #define DMAC_CHCR10 0xFC81807C
227 #define DMAC_SAR11 0xFC818080
228 #define DMAC_DAR11 0xFC818084
229 #define DMAC_TCR11 0xFC818088
230 #define DMAC_CHCR11 0xFC81808C
231 #define DMAC_SARB6 0xFC818120
232 #define DMAC_DARB6 0xFC818124
233 #define DMAC_TCRB6 0xFC818128
234 #define DMAC_SARB7 0xFC818130
235 #define DMAC_DARB7 0xFC818134
236 #define DMAC_TCRB7 0xFC818138
237 #define DMAC_SARB8 0xFC818140
238 #define DMAC_DARB8 0xFC818144
239 #define DMAC_TCRB8 0xFC818148
240 #define DMAC_SARB9 0xFC818150
241 #define DMAC_DARB9 0xFC818154
242 #define DMAC_TCRB9 0xFC818158
244 /* Clock Pulse Generator */
245 #define FRQCR 0xFFC80000
246 #define PLLCR 0xFFC80024
247 #define MSTPCR 0xFFC80030
249 /* Watchdog Timer and Reset */
251 #define WDTST 0xFFCC0000
252 #define WDTCSR 0xFFCC0004
253 #define WDTBST 0xFFCC0008
254 #define WDTCNT 0xFFCC0010
255 #define WDTBCNT 0xFFCC0018
258 #define MSTPCR 0xFFC80030
261 #define TMU_BASE 0xFFD80000
264 #define CMTCFG 0xFFE30000
265 #define CMTFRT 0xFFE30004
266 #define CMTCTL 0xFFE30008
267 #define CMTIRQS 0xFFE3000C
268 #define CMTCH0T 0xFFE30010
269 #define CMTCH0ST 0xFFE30020
270 #define CMTCH0C 0xFFE30030
271 #define CMTCH1T 0xFFE30014
272 #define CMTCH1ST 0xFFE30024
273 #define CMTCH1C 0xFFE30034
274 #define CMTCH2T 0xFFE30018
275 #define CMTCH2C 0xFFE30038
276 #define CMTCH3T 0xFFE3001C
277 #define CMTCH3C 0xFFE3003C
280 #define R64CNT 0xFFE80000
281 #define RSECCNT 0xFFE80004
282 #define RMINCNT 0xFFE80008
283 #define RHRCNT 0xFFE8000C
284 #define RWKCNT 0xFFE80010
285 #define RDAYCNT 0xFFE80014
286 #define RMONCNT 0xFFE80018
287 #define RYRCNT 0xFFE8001C
288 #define RSECAR 0xFFE80020
289 #define RMINAR 0xFFE80024
290 #define RHRAR 0xFFE80028
291 #define RWKAR 0xFFE8002C
292 #define RDAYAR 0xFFE80030
293 #define RMONAR 0xFFE80034
294 #define RCR1 0xFFE80038
295 #define RCR2 0xFFE8003C
296 #define RCR3 0xFFE80050
297 #define RYRAR 0xFFE80054
299 /* Serial Communication Interface with FIFO */
300 #define SCSMR0 0xFFE00000
301 #define SCIF0_BASE SCSMR0
303 /* Serial I/O with FIFO */
304 #define SIMDR 0xFFE20000
305 #define SISCR 0xFFE20002
306 #define SITDAR 0xFFE20004
307 #define SIRDAR 0xFFE20006
308 #define SICDAR 0xFFE20008
309 #define SICTR 0xFFE2000C
310 #define SIFCTR 0xFFE20010
311 #define SISTR 0xFFE20014
312 #define SIIER 0xFFE20016
313 #define SITCR 0xFFE20028
314 #define SIRCR 0xFFE2002C
315 #define SPICR 0xFFE20030
317 /* Serial Protocol Interface */
318 #define SPCR 0xFFE50000
319 #define SPSR 0xFFE50004
320 #define SPSCR 0xFFE50008
321 #define SPTBR 0xFFE5000C
322 #define SPRBR 0xFFE50010
324 /* Multimedia Card Interface */
325 #define CMDR0 0xFFE60000
326 #define CMDR1 0xFFE60001
327 #define CMDR2 0xFFE60002
328 #define CMDR3 0xFFE60003
329 #define CMDR4 0xFFE60004
330 #define CMDR5 0xFFE60005
331 #define CMDSTRT 0xFFE60006
332 #define OPCR 0xFFE6000A
333 #define CSTR 0xFFE6000B
334 #define INTCR0 0xFFE6000C
335 #define INTCR1 0xFFE6000D
336 #define INTSTR0 0xFFE6000E
337 #define INTSTR1 0xFFE6000F
338 #define CLKON 0xFFE60010
339 #define CTOCR 0xFFE60011
340 #define TBCR 0xFFE60014
341 #define MODER 0xFFE60016
342 #define CMDTYR 0xFFE60018
343 #define RSPTYR 0xFFE60019
344 #define TBNCR 0xFFE6001A
345 #define RSPR0 0xFFE60020
346 #define RSPR1 0xFFE60021
347 #define RSPR2 0xFFE60022
348 #define RSPR3 0xFFE60023
349 #define RSPR4 0xFFE60024
350 #define RSPR5 0xFFE60025
351 #define RSPR6 0xFFE60026
352 #define RSPR7 0xFFE60027
353 #define RSPR8 0xFFE60028
354 #define RSPR9 0xFFE60029
355 #define RSPR10 0xFFE6002A
356 #define RSPR11 0xFFE6002B
357 #define RSPR12 0xFFE6002C
358 #define RSPR13 0xFFE6002D
359 #define RSPR14 0xFFE6002E
360 #define RSPR15 0xFFE6002F
361 #define RSPR16 0xFFE60030
362 #define RSPRD 0xFFE60031
363 #define DTOUTR 0xFFE60032
364 #define DR 0xFFE60040
365 #define DMACR 0xFFE60044
366 #define INTCR2 0xFFE60046
367 #define INTSTR2 0xFFE60048
369 /* Audio Codec Interface */
370 #define HACCR 0xFFE40008
371 #define HACCSAR 0xFFE40020
372 #define HACCSDR 0xFFE40024
373 #define HACPCML 0xFFE40028
374 #define HACPCMR 0xFFE4002C
375 #define HACTIER 0xFFE40050
376 #define HACTSR 0xFFE40054
377 #define HACRIER 0xFFE40058
378 #define HACRSR 0xFFE4005C
379 #define HACACR 0xFFE40060
381 /* Serial Sound Interface */
382 #define SSICR 0xFFE70000
383 #define SSISR 0xFFE70004
384 #define SSITDR 0xFFE70008
385 #define SSIRDR 0xFFE7000C
387 /* Flash memory Controller */
388 #define FLCMNCR 0xFFE90000
389 #define FLCMDCR 0xFFE90004
390 #define FLCMCDR 0xFFE90008
391 #define FLADR 0xFFE9000C
392 #define FLDATAR 0xFFE90010
393 #define FLDTCNTR 0xFFE90014
394 #define FLINTDMACR 0xFFE90018
395 #define FLBSYTMR 0xFFE9001C
396 #define FLBSYCNT 0xFFE90020
397 #define FLTRCR 0xFFE9002C
399 /* General Purpose I/O */
400 #define PACR 0xFFEA0000
401 #define PBCR 0xFFEA0002
402 #define PCCR 0xFFEA0004
403 #define PDCR 0xFFEA0006
404 #define PECR 0xFFEA0008
405 #define PFCR 0xFFEA000A
406 #define PGCR 0xFFEA000C
407 #define PHCR 0xFFEA000E
408 #define PJCR 0xFFEA0010
409 #define PKCR 0xFFEA0012
410 #define PLCR 0xFFEA0014
411 #define PMCR 0xFFEA0016
412 #define PADR 0xFFEA0020
413 #define PBDR 0xFFEA0022
414 #define PCDR 0xFFEA0024
415 #define PDDR 0xFFEA0026
416 #define PEDR 0xFFEA0028
417 #define PFDR 0xFFEA002A
418 #define PGDR 0xFFEA002C
419 #define PHDR 0xFFEA002E
420 #define PJDR 0xFFEA0030
421 #define PKDR 0xFFEA0032
422 #define PLDR 0xFFEA0034
423 #define PMDR 0xFFEA0036
424 #define PEPUPR 0xFFEA0048
425 #define PHPUPR 0xFFEA004E
426 #define PJPUPR 0xFFEA0050
427 #define PKPUPR 0xFFEA0052
428 #define PMPUPR 0xFFEA0056
429 #define PPUPR1 0xFFEA0060
430 #define PPUPR2 0xFFEA0062
431 #define PMSELR 0xFFEA0080
433 /* User Break Controller */
434 #define CBR0 0xFF200000
435 #define CRR0 0xFF200004
436 #define CAR0 0xFF200008
437 #define CAMR0 0xFF20000C
438 #define CBR1 0xFF200020
439 #define CRR1 0xFF200024
440 #define CAR1 0xFF200028
441 #define CAMR1 0xFF20002C
442 #define CDR1 0xFF200030
443 #define CDMR1 0xFF200034
444 #define CETR1 0xFF200038
445 #define CCMFR 0xFF200600
446 #define CBCR 0xFF200620
448 #endif /* _ASM_CPU_SH7780_H_ */