1 #ifndef _ASM_CPU_SH7785_H_
2 #define _ASM_CPU_SH7785_H_
5 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
7 * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define CACHE_OC_NUM_WAYS 1
27 #define CCR_CACHE_INIT 0x0000090b
30 #define TRA 0xFF000020
31 #define EXPEVT 0xFF000024
32 #define INTEVT 0xFF000028
34 /* Cache Controller */
35 #define CCR 0xFF00001C
36 #define QACR0 0xFF000038
37 #define QACR1 0xFF00003C
38 #define RAMCR 0xFF000074
40 /* Watchdog Timer and Reset */
42 #define WDTST 0xFFCC0000
43 #define WDTCSR 0xFFCC0004
44 #define WDTBST 0xFFCC0008
45 #define WDTCNT 0xFFCC0010
46 #define WDTBCNT 0xFFCC0018
49 #define TMU_BASE 0xFFD80000
51 /* Serial Communication Interface with FIFO */
52 #define SCIF1_BASE 0xffeb0000
55 #define MMSELR 0xfc400020
56 #define LBSC_BASE 0xff800000
57 #define BCR (LBSC_BASE + 0x1000)
58 #define CS0BCR (LBSC_BASE + 0x2000)
59 #define CS1BCR (LBSC_BASE + 0x2010)
60 #define CS2BCR (LBSC_BASE + 0x2020)
61 #define CS3BCR (LBSC_BASE + 0x2030)
62 #define CS4BCR (LBSC_BASE + 0x2040)
63 #define CS5BCR (LBSC_BASE + 0x2050)
64 #define CS6BCR (LBSC_BASE + 0x2060)
65 #define CS0WCR (LBSC_BASE + 0x2008)
66 #define CS1WCR (LBSC_BASE + 0x2018)
67 #define CS2WCR (LBSC_BASE + 0x2028)
68 #define CS3WCR (LBSC_BASE + 0x2038)
69 #define CS4WCR (LBSC_BASE + 0x2048)
70 #define CS5WCR (LBSC_BASE + 0x2058)
71 #define CS6WCR (LBSC_BASE + 0x2068)
72 #define CS5PCR (LBSC_BASE + 0x2070)
73 #define CS6PCR (LBSC_BASE + 0x2080)
76 #define SH7780_PCIECR 0xFE000008
77 #define SH7780_PCIVID 0xFE040000
78 #define SH7780_PCIDID 0xFE040002
79 #define SH7780_PCICMD 0xFE040004
80 #define SH7780_PCISTATUS 0xFE040006
81 #define SH7780_PCIRID 0xFE040008
82 #define SH7780_PCIPIF 0xFE040009
83 #define SH7780_PCISUB 0xFE04000A
84 #define SH7780_PCIBCC 0xFE04000B
85 #define SH7780_PCICLS 0xFE04000C
86 #define SH7780_PCILTM 0xFE04000D
87 #define SH7780_PCIHDR 0xFE04000E
88 #define SH7780_PCIBIST 0xFE04000F
89 #define SH7780_PCIIBAR 0xFE040010
90 #define SH7780_PCIMBAR0 0xFE040014
91 #define SH7780_PCIMBAR1 0xFE040018
92 #define SH7780_PCISVID 0xFE04002C
93 #define SH7780_PCISID 0xFE04002E
94 #define SH7780_PCICP 0xFE040034
95 #define SH7780_PCIINTLINE 0xFE04003C
96 #define SH7780_PCIINTPIN 0xFE04003D
97 #define SH7780_PCIMINGNT 0xFE04003E
98 #define SH7780_PCIMAXLAT 0xFE04003F
99 #define SH7780_PCICID 0xFE040040
100 #define SH7780_PCINIP 0xFE040041
101 #define SH7780_PCIPMC 0xFE040042
102 #define SH7780_PCIPMCSR 0xFE040044
103 #define SH7780_PCIPMCSRBSE 0xFE040046
104 #define SH7780_PCI_CDD 0xFE040047
105 #define SH7780_PCICR 0xFE040100
106 #define SH7780_PCILSR0 0xFE040104
107 #define SH7780_PCILSR1 0xFE040108
108 #define SH7780_PCILAR0 0xFE04010C
109 #define SH7780_PCILAR1 0xFE040110
110 #define SH7780_PCIIR 0xFE040114
111 #define SH7780_PCIIMR 0xFE040118
112 #define SH7780_PCIAIR 0xFE04011C
113 #define SH7780_PCICIR 0xFE040120
114 #define SH7780_PCIAINT 0xFE040130
115 #define SH7780_PCIAINTM 0xFE040134
116 #define SH7780_PCIBMIR 0xFE040138
117 #define SH7780_PCIPAR 0xFE0401C0
118 #define SH7780_PCIPINT 0xFE0401CC
119 #define SH7780_PCIPINTM 0xFE0401D0
120 #define SH7780_PCIMBR0 0xFE0401E0
121 #define SH7780_PCIMBMR0 0xFE0401E4
122 #define SH7780_PCIMBR1 0xFE0401E8
123 #define SH7780_PCIMBMR1 0xFE0401EC
124 #define SH7780_PCIMBR2 0xFE0401F0
125 #define SH7780_PCIMBMR2 0xFE0401F4
126 #define SH7780_PCIIOBR 0xFE0401F8
127 #define SH7780_PCIIOBMR 0xFE0401FC
128 #define SH7780_PCICSCR0 0xFE040210
129 #define SH7780_PCICSCR1 0xFE040214
130 #define SH7780_PCICSAR0 0xFE040218
131 #define SH7780_PCICSAR1 0xFE04021C
132 #define SH7780_PCIPDR 0xFE040220
134 #endif /* _ASM_CPU_SH7780_H_ */