1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
7 !! libgcc routines for the Renesas / SuperH SH CPUs.
8 !! Contributed by Steve Chamberlain.
11 !! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
12 !! recoded in assembly by Toshiyasu Morita
15 /* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
16 ELF local label prefixes by J"orn Rennecke
19 /* This code used shld, thus is not suitable for SH1 / SH2. */
21 /* Signed / unsigned division without use of FPU, optimized for SH4.
22 Uses a lookup table for divisors in the range -128 .. +128, and
23 div1 with case distinction for larger divisors in three more ranges.
24 The code is lumped together with the table to allow the use of mova. */
25 #ifdef CONFIG_CPU_LITTLE_ENDIAN
38 .set __udivsi3_i4, __udivsi3_i4i
39 .type __udivsi3_i4i, @function
120 mov.b r0,@(L_LSWMSB,r15)
153 .global __sdivsi3_i4i
156 .set __sdivsi3_i4, __sdivsi3_i4i
157 .set __sdivsi3, __sdivsi3_i4i
158 .type __sdivsi3_i4i, @function
159 /* This is link-compatible with a __sdivsi3 call,
160 but we effectively clobber only r1. */
193 mov.b r0,@(L_MSWLSB,r15)
199 mov.b r0,@(L_LSWMSB,r15)
204 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
216 mova div_table_inv,r0
219 mova div_table_clz,r0
253 mov.b r0,@(L_MSWLSB,r15)
259 mov.b r0,@(L_LSWMSB,r15)
264 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
286 mov.b r0,@(L_LSWMSB,r15)
289 bra div_ge64k_neg_end
311 /* This table has been generated by divtab-sh4.c. */
442 /* Lookup table translating positive divisor to index into table of
443 normalized inverse. N.B. the '0' entry is also the last entry of the
444 previous table, and causes an unaligned access for division by zero. */
575 /* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
643 /* maximum error: 0.987342 scaled: 0.921875*/