1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
14 config VENDOR_EMULATION
25 # board-specific options below
26 source "board/coreboot/Kconfig"
27 source "board/emulation/Kconfig"
28 source "board/google/Kconfig"
29 source "board/intel/Kconfig"
31 # platform-specific options below
32 source "arch/x86/cpu/baytrail/Kconfig"
33 source "arch/x86/cpu/coreboot/Kconfig"
34 source "arch/x86/cpu/ivybridge/Kconfig"
35 source "arch/x86/cpu/qemu/Kconfig"
36 source "arch/x86/cpu/quark/Kconfig"
37 source "arch/x86/cpu/queensbay/Kconfig"
39 # architecture-specific options below
41 config SYS_MALLOC_F_LEN
50 depends on X86_RESET_VECTOR
59 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
68 config X86_RESET_VECTOR
72 config SYS_X86_START16
74 depends on X86_RESET_VECTOR
77 config BOARD_ROMSIZE_KB_512
79 config BOARD_ROMSIZE_KB_1024
81 config BOARD_ROMSIZE_KB_2048
83 config BOARD_ROMSIZE_KB_4096
85 config BOARD_ROMSIZE_KB_8192
87 config BOARD_ROMSIZE_KB_16384
91 prompt "ROM chip size"
92 depends on X86_RESET_VECTOR
93 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
94 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
95 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
96 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
97 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
98 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
100 Select the size of the ROM chip you intend to flash U-Boot on.
102 The build system will take care of creating a u-boot.rom file
103 of the matching size.
105 config UBOOT_ROMSIZE_KB_512
108 Choose this option if you have a 512 KB ROM chip.
110 config UBOOT_ROMSIZE_KB_1024
111 bool "1024 KB (1 MB)"
113 Choose this option if you have a 1024 KB (1 MB) ROM chip.
115 config UBOOT_ROMSIZE_KB_2048
116 bool "2048 KB (2 MB)"
118 Choose this option if you have a 2048 KB (2 MB) ROM chip.
120 config UBOOT_ROMSIZE_KB_4096
121 bool "4096 KB (4 MB)"
123 Choose this option if you have a 4096 KB (4 MB) ROM chip.
125 config UBOOT_ROMSIZE_KB_8192
126 bool "8192 KB (8 MB)"
128 Choose this option if you have a 8192 KB (8 MB) ROM chip.
130 config UBOOT_ROMSIZE_KB_16384
131 bool "16384 KB (16 MB)"
133 Choose this option if you have a 16384 KB (16 MB) ROM chip.
137 # Map the config names to an integer (KB).
138 config UBOOT_ROMSIZE_KB
140 default 512 if UBOOT_ROMSIZE_KB_512
141 default 1024 if UBOOT_ROMSIZE_KB_1024
142 default 2048 if UBOOT_ROMSIZE_KB_2048
143 default 4096 if UBOOT_ROMSIZE_KB_4096
144 default 8192 if UBOOT_ROMSIZE_KB_8192
145 default 16384 if UBOOT_ROMSIZE_KB_16384
147 # Map the config names to a hex value (bytes).
150 default 0x80000 if UBOOT_ROMSIZE_KB_512
151 default 0x100000 if UBOOT_ROMSIZE_KB_1024
152 default 0x200000 if UBOOT_ROMSIZE_KB_2048
153 default 0x400000 if UBOOT_ROMSIZE_KB_4096
154 default 0x800000 if UBOOT_ROMSIZE_KB_8192
155 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
156 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
159 bool "Platform requires Intel Management Engine"
161 Newer higher-end devices have an Intel Management Engine (ME)
162 which is a very large binary blob (typically 1.5MB) which is
163 required for the platform to work. This enforces a particular
164 SPI flash format. You will need to supply the me.bin file in
165 your board directory.
168 bool "Perform a simple RAM test after SDRAM initialisation"
170 If there is something wrong with SDRAM then the platform will
171 often crash within U-Boot or the kernel. This option enables a
172 very simple RAM test that quickly checks whether the SDRAM seems
173 to work correctly. It is not exhaustive but can save time by
174 detecting obvious failures.
176 config MARK_GRAPHICS_MEM_WRCOMB
177 bool "Mark graphics memory as write-combining"
180 The graphics performance may increase if the graphics
181 memory is set as write-combining cache type. This option
182 enables marking the graphics memory as write-combining.
185 bool "Add an Firmware Support Package binary"
187 Select this option to add an Firmware Support Package binary to
188 the resulting U-Boot image. It is a binary blob which U-Boot uses
189 to set up SDRAM and other chipset specific initialization.
191 Note: Without this binary U-Boot will not be able to set up its
192 SDRAM so will not boot.
195 string "Firmware Support Package binary filename"
199 The filename of the file to use as Firmware Support Package binary
200 in the board directory.
203 hex "Firmware Support Package binary location"
207 FSP is not Position Independent Code (PIC) and the whole FSP has to
208 be rebased if it is placed at a location which is different from the
209 perferred base address specified during the FSP build. Use Intel's
210 Binary Configuration Tool (BCT) to do the rebase.
212 The default base address of 0xfffc0000 indicates that the binary must
213 be located at offset 0xc0000 from the beginning of a 1MB flash device.
215 config FSP_TEMP_RAM_ADDR
220 Stack top address which is used in FspInit after DRAM is ready and
224 int "Maximum number of CPUs permitted"
227 When using multi-CPU chips it is possible for U-Boot to start up
228 more than one CPU. The stack memory used by all of these CPUs is
229 pre-allocated so at present U-Boot wants to know the maximum
230 number of CPUs that may be present. Set this to at least as high
231 as the number of CPUs in your system (it uses about 4KB of RAM for
235 bool "Enable Symmetric Multiprocessing"
238 Enable use of more than one CPU in U-Boot and the Operating System
239 when loaded. Each CPU will be started up and information can be
240 obtained using the 'cpu' command. If this option is disabled, then
241 only one CPU will be enabled regardless of the number of CPUs
248 Each additional CPU started by U-Boot requires its own stack. This
249 option sets the stack size used by each CPU and directly affects
250 the memory used by this initialisation process. Typically 4KB is
253 config TSC_CALIBRATION_BYPASS
254 bool "Bypass Time-Stamp Counter (TSC) calibration"
257 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
258 running frequency via Model-Specific Register (MSR) and Programmable
259 Interval Timer (PIT). If the calibration does not work on your board,
260 select this option and provide a hardcoded TSC running frequency with
261 CONFIG_TSC_FREQ_IN_MHZ below.
263 Normally this option should be turned on in a simulation environment
266 config TSC_FREQ_IN_MHZ
267 int "Time-Stamp Counter (TSC) running frequency in MHz"
268 depends on TSC_CALIBRATION_BYPASS
271 The running frequency in MHz of Time-Stamp Counter (TSC).
275 config GENERATE_PIRQ_TABLE
276 bool "Generate a PIRQ table"
279 Generate a PIRQ routing table for this board. The PIRQ routing table
280 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
281 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
282 It specifies the interrupt router information as well how all the PCI
283 devices' interrupt pins are wired to PIRQs.
285 config GENERATE_SFI_TABLE
286 bool "Generate a SFI (Simple Firmware Interface) table"
288 The Simple Firmware Interface (SFI) provides a lightweight method
289 for platform firmware to pass information to the operating system
290 via static tables in memory. Kernel SFI support is required to
291 boot on SFI-only platforms. If you have ACPI tables then these are
294 U-Boot writes this table in write_sfi_table() just before booting
297 For more information, see http://simplefirmware.org
301 config MAX_PIRQ_LINKS
305 This variable specifies the number of PIRQ interrupt links which are
306 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
307 Some newer chipsets offer more than four links, commonly up to PIRQH.
309 config IRQ_SLOT_COUNT
313 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
314 which in turns forms a table of exact 4KiB. The default value 128
315 should be enough for most boards. If this does not fit your board,
316 change it according to your needs.
318 config PCIE_ECAM_BASE
322 This is the memory-mapped address of PCI configuration space, which
323 is only available through the Enhanced Configuration Access
324 Mechanism (ECAM) with PCI Express. It can be set up almost
325 anywhere. Before it is set up, it is possible to access PCI
326 configuration space through I/O access, but memory access is more
327 convenient. Using this, PCI can be scanned and configured. This
328 should be set to a region that does not conflict with memory
329 assigned to PCI devices - i.e. the memory and prefetch regions, as
330 passed to pci_set_region().