1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_ADVANTECH
14 config VENDOR_CONGATEC
17 config VENDOR_COREBOOT
23 config VENDOR_EMULATION
34 # board-specific options below
35 source "board/advantech/Kconfig"
36 source "board/congatec/Kconfig"
37 source "board/coreboot/Kconfig"
38 source "board/efi/Kconfig"
39 source "board/emulation/Kconfig"
40 source "board/google/Kconfig"
41 source "board/intel/Kconfig"
43 # platform-specific options below
44 source "arch/x86/cpu/baytrail/Kconfig"
45 source "arch/x86/cpu/broadwell/Kconfig"
46 source "arch/x86/cpu/coreboot/Kconfig"
47 source "arch/x86/cpu/ivybridge/Kconfig"
48 source "arch/x86/cpu/qemu/Kconfig"
49 source "arch/x86/cpu/quark/Kconfig"
50 source "arch/x86/cpu/queensbay/Kconfig"
52 # architecture-specific options below
57 config SYS_MALLOC_F_LEN
66 depends on X86_RESET_VECTOR
75 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
84 config X86_RESET_VECTOR
88 config RESET_SEG_START
90 depends on X86_RESET_VECTOR
95 depends on X86_RESET_VECTOR
100 depends on X86_RESET_VECTOR
103 config SYS_X86_START16
105 depends on X86_RESET_VECTOR
108 config BOARD_ROMSIZE_KB_512
110 config BOARD_ROMSIZE_KB_1024
112 config BOARD_ROMSIZE_KB_2048
114 config BOARD_ROMSIZE_KB_4096
116 config BOARD_ROMSIZE_KB_8192
118 config BOARD_ROMSIZE_KB_16384
122 prompt "ROM chip size"
123 depends on X86_RESET_VECTOR
124 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
125 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
126 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
127 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
128 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
129 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
131 Select the size of the ROM chip you intend to flash U-Boot on.
133 The build system will take care of creating a u-boot.rom file
134 of the matching size.
136 config UBOOT_ROMSIZE_KB_512
139 Choose this option if you have a 512 KB ROM chip.
141 config UBOOT_ROMSIZE_KB_1024
142 bool "1024 KB (1 MB)"
144 Choose this option if you have a 1024 KB (1 MB) ROM chip.
146 config UBOOT_ROMSIZE_KB_2048
147 bool "2048 KB (2 MB)"
149 Choose this option if you have a 2048 KB (2 MB) ROM chip.
151 config UBOOT_ROMSIZE_KB_4096
152 bool "4096 KB (4 MB)"
154 Choose this option if you have a 4096 KB (4 MB) ROM chip.
156 config UBOOT_ROMSIZE_KB_8192
157 bool "8192 KB (8 MB)"
159 Choose this option if you have a 8192 KB (8 MB) ROM chip.
161 config UBOOT_ROMSIZE_KB_16384
162 bool "16384 KB (16 MB)"
164 Choose this option if you have a 16384 KB (16 MB) ROM chip.
168 # Map the config names to an integer (KB).
169 config UBOOT_ROMSIZE_KB
171 default 512 if UBOOT_ROMSIZE_KB_512
172 default 1024 if UBOOT_ROMSIZE_KB_1024
173 default 2048 if UBOOT_ROMSIZE_KB_2048
174 default 4096 if UBOOT_ROMSIZE_KB_4096
175 default 8192 if UBOOT_ROMSIZE_KB_8192
176 default 16384 if UBOOT_ROMSIZE_KB_16384
178 # Map the config names to a hex value (bytes).
181 default 0x80000 if UBOOT_ROMSIZE_KB_512
182 default 0x100000 if UBOOT_ROMSIZE_KB_1024
183 default 0x200000 if UBOOT_ROMSIZE_KB_2048
184 default 0x400000 if UBOOT_ROMSIZE_KB_4096
185 default 0x800000 if UBOOT_ROMSIZE_KB_8192
186 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
187 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
190 bool "Platform requires Intel Management Engine"
192 Newer higher-end devices have an Intel Management Engine (ME)
193 which is a very large binary blob (typically 1.5MB) which is
194 required for the platform to work. This enforces a particular
195 SPI flash format. You will need to supply the me.bin file in
196 your board directory.
199 bool "Perform a simple RAM test after SDRAM initialisation"
201 If there is something wrong with SDRAM then the platform will
202 often crash within U-Boot or the kernel. This option enables a
203 very simple RAM test that quickly checks whether the SDRAM seems
204 to work correctly. It is not exhaustive but can save time by
205 detecting obvious failures.
208 bool "Add an Firmware Support Package binary"
211 Select this option to add an Firmware Support Package binary to
212 the resulting U-Boot image. It is a binary blob which U-Boot uses
213 to set up SDRAM and other chipset specific initialization.
215 Note: Without this binary U-Boot will not be able to set up its
216 SDRAM so will not boot.
219 string "Firmware Support Package binary filename"
223 The filename of the file to use as Firmware Support Package binary
224 in the board directory.
227 hex "Firmware Support Package binary location"
231 FSP is not Position Independent Code (PIC) and the whole FSP has to
232 be rebased if it is placed at a location which is different from the
233 perferred base address specified during the FSP build. Use Intel's
234 Binary Configuration Tool (BCT) to do the rebase.
236 The default base address of 0xfffc0000 indicates that the binary must
237 be located at offset 0xc0000 from the beginning of a 1MB flash device.
239 config FSP_TEMP_RAM_ADDR
244 Stack top address which is used in fsp_init() after DRAM is ready and
247 config FSP_SYS_MALLOC_F_LEN
252 Additional size of malloc() pool before relocation.
259 Most FSPs use UPD data region for some FSP customization. But there
260 are still some FSPs that might not even have UPD. For such FSPs,
261 override this to n in their platform Kconfig files.
263 config FSP_BROKEN_HOB
267 Indicate some buggy FSPs that does not report memory used by FSP
268 itself as reserved in the resource descriptor HOB. Select this to
269 tell U-Boot to do some additional work to ensure U-Boot relocation
270 do not overwrite the important boot service data which is used by
271 FSP, otherwise the subsequent call to fsp_notify() will fail.
273 config ENABLE_MRC_CACHE
274 bool "Enable MRC cache"
275 depends on !EFI && !SYS_COREBOOT
277 Enable this feature to cause MRC data to be cached in NV storage
278 to be used for speeding up boot time on future reboots and/or
281 For platforms that use Intel FSP for the memory initialization,
282 please check FSP output HOB via U-Boot command 'fsp hob' to see
283 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
284 If such GUID does not exist, MRC cache is not avaiable on such
285 platform (eg: Intel Queensbay), which means selecting this option
286 here does not make any difference.
289 bool "Add a System Agent binary"
292 Select this option to add a System Agent binary to
293 the resulting U-Boot image. MRC stands for Memory Reference Code.
294 It is a binary blob which U-Boot uses to set up SDRAM.
296 Note: Without this binary U-Boot will not be able to set up its
297 SDRAM so will not boot.
304 Enable caching for the memory reference code binary. This uses an
305 MTRR (memory type range register) to turn on caching for the section
306 of SPI flash that contains the memory reference code. This makes
307 SDRAM init run faster.
309 config CACHE_MRC_SIZE_KB
314 Sets the size of the cached area for the memory reference code.
315 This ends at the end of SPI flash (address 0xffffffff) and is
316 measured in KB. Typically this is set to 512, providing for 0.5MB
319 config DCACHE_RAM_BASE
323 Sets the base of the data cache area in memory space. This is the
324 start address of the cache-as-RAM (CAR) area and the address varies
325 depending on the CPU. Once CAR is set up, read/write memory becomes
326 available at this address and can be used temporarily until SDRAM
329 config DCACHE_RAM_SIZE
334 Sets the total size of the data cache area in memory space. This
335 sets the size of the cache-as-RAM (CAR) area. Note that much of the
336 CAR space is required by the MRC. The CAR space available to U-Boot
337 is normally at the start and typically extends to 1/4 or 1/2 of the
340 config DCACHE_RAM_MRC_VAR_SIZE
344 This is the amount of CAR (Cache as RAM) reserved for use by the
345 memory reference code. This depends on the implementation of the
346 memory reference code and must be set correctly or the board will
350 bool "Add a Reference Code binary"
352 Select this option to add a Reference Code binary to the resulting
353 U-Boot image. This is an Intel binary blob that handles system
354 initialisation, in this case the PCH and System Agent.
356 Note: Without this binary (on platforms that need it such as
357 broadwell) U-Boot will be missing some critical setup steps.
358 Various peripherals may fail to work.
361 bool "Enable Symmetric Multiprocessing"
364 Enable use of more than one CPU in U-Boot and the Operating System
365 when loaded. Each CPU will be started up and information can be
366 obtained using the 'cpu' command. If this option is disabled, then
367 only one CPU will be enabled regardless of the number of CPUs
371 int "Maximum number of CPUs permitted"
375 When using multi-CPU chips it is possible for U-Boot to start up
376 more than one CPU. The stack memory used by all of these CPUs is
377 pre-allocated so at present U-Boot wants to know the maximum
378 number of CPUs that may be present. Set this to at least as high
379 as the number of CPUs in your system (it uses about 4KB of RAM for
387 Each additional CPU started by U-Boot requires its own stack. This
388 option sets the stack size used by each CPU and directly affects
389 the memory used by this initialisation process. Typically 4KB is
393 bool "Add a VGA BIOS image"
395 Select this option if you have a VGA BIOS image that you would
396 like to add to your ROM.
399 string "VGA BIOS image filename"
400 depends on HAVE_VGA_BIOS
403 The filename of the VGA BIOS image in the board directory.
406 hex "VGA BIOS image location"
407 depends on HAVE_VGA_BIOS
410 The location of VGA BIOS image in the SPI flash. For example, base
411 address of 0xfff90000 indicates that the image will be put at offset
412 0x90000 from the beginning of a 1MB flash device.
415 depends on !EFI && !SYS_COREBOOT
417 config GENERATE_PIRQ_TABLE
418 bool "Generate a PIRQ table"
421 Generate a PIRQ routing table for this board. The PIRQ routing table
422 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
423 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
424 It specifies the interrupt router information as well how all the PCI
425 devices' interrupt pins are wired to PIRQs.
427 config GENERATE_SFI_TABLE
428 bool "Generate a SFI (Simple Firmware Interface) table"
430 The Simple Firmware Interface (SFI) provides a lightweight method
431 for platform firmware to pass information to the operating system
432 via static tables in memory. Kernel SFI support is required to
433 boot on SFI-only platforms. If you have ACPI tables then these are
436 U-Boot writes this table in write_sfi_table() just before booting
439 For more information, see http://simplefirmware.org
441 config GENERATE_MP_TABLE
442 bool "Generate an MP (Multi-Processor) table"
445 Generate an MP (Multi-Processor) table for this board. The MP table
446 provides a way for the operating system to support for symmetric
447 multiprocessing as well as symmetric I/O interrupt handling with
448 the local APIC and I/O APIC.
450 config GENERATE_ACPI_TABLE
451 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
455 The Advanced Configuration and Power Interface (ACPI) specification
456 provides an open standard for device configuration and management
457 by the operating system. It defines platform-independent interfaces
458 for configuration and power management monitoring.
460 config GENERATE_SMBIOS_TABLE
461 bool "Generate an SMBIOS (System Management BIOS) table"
464 The System Management BIOS (SMBIOS) specification addresses how
465 motherboard and system vendors present management information about
466 their products in a standard format by extending the BIOS interface
467 on Intel architecture systems.
469 Check http://www.dmtf.org/standards/smbios for details.
471 config SMBIOS_MANUFACTURER
472 string "SMBIOS Manufacturer"
473 depends on GENERATE_SMBIOS_TABLE
476 The board manufacturer to store in SMBIOS structures.
477 Change this to override the default one (CONFIG_SYS_VENDOR).
479 config SMBIOS_PRODUCT_NAME
480 string "SMBIOS Product Name"
481 depends on GENERATE_SMBIOS_TABLE
484 The product name to store in SMBIOS structures.
485 Change this to override the default one (CONFIG_SYS_BOARD).
489 config MAX_PIRQ_LINKS
493 This variable specifies the number of PIRQ interrupt links which are
494 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
495 Some newer chipsets offer more than four links, commonly up to PIRQH.
497 config IRQ_SLOT_COUNT
501 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
502 which in turns forms a table of exact 4KiB. The default value 128
503 should be enough for most boards. If this does not fit your board,
504 change it according to your needs.
506 config PCIE_ECAM_BASE
510 This is the memory-mapped address of PCI configuration space, which
511 is only available through the Enhanced Configuration Access
512 Mechanism (ECAM) with PCI Express. It can be set up almost
513 anywhere. Before it is set up, it is possible to access PCI
514 configuration space through I/O access, but memory access is more
515 convenient. Using this, PCI can be scanned and configured. This
516 should be set to a region that does not conflict with memory
517 assigned to PCI devices - i.e. the memory and prefetch regions, as
518 passed to pci_set_region().
520 config PCIE_ECAM_SIZE
524 This is the size of memory-mapped address of PCI configuration space,
525 which is only available through the Enhanced Configuration Access
526 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
527 so a default 0x10000000 size covers all of the 256 buses which is the
528 maximum number of PCI buses as defined by the PCI specification.
534 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
535 slave) interrupt controllers. Include this to have U-Boot set up
536 the interrupt correctly.
542 Intel 8254 timer contains three counters which have fixed uses.
543 Include this to have U-Boot set up the timer correctly.
552 bool "Support booting SeaBIOS"
554 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
555 It can run in an emulator or natively on X86 hardware with the use
556 of coreboot/U-Boot. By turning on this option, U-Boot prepares
557 all the configuration tables that are necessary to boot SeaBIOS.
559 Check http://www.seabios.org/SeaBIOS for details.
561 config HIGH_TABLE_SIZE
562 hex "Size of configuration tables which reside in high memory"
566 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
567 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
568 puts a copy of configuration tables in high memory region which
569 is reserved on the stack before relocation. The region size is
570 determined by this option.
572 Increse it if the default size does not fit the board's needs.
573 This is most likely due to a large ACPI DSDT table is used.
575 source "arch/x86/lib/efi/Kconfig"