1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
14 prompt "Mainboard vendor"
15 default VENDOR_EMULATION
17 config VENDOR_COREBOOT
20 config VENDOR_EMULATION
31 # board-specific options below
32 source "board/coreboot/Kconfig"
33 source "board/emulation/Kconfig"
34 source "board/google/Kconfig"
35 source "board/intel/Kconfig"
37 # platform-specific options below
38 source "arch/x86/cpu/baytrail/Kconfig"
39 source "arch/x86/cpu/coreboot/Kconfig"
40 source "arch/x86/cpu/ivybridge/Kconfig"
41 source "arch/x86/cpu/qemu/Kconfig"
42 source "arch/x86/cpu/quark/Kconfig"
43 source "arch/x86/cpu/queensbay/Kconfig"
45 # architecture-specific options below
47 config SYS_MALLOC_F_LEN
56 depends on X86_RESET_VECTOR
65 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
74 config X86_RESET_VECTOR
78 config SYS_X86_START16
80 depends on X86_RESET_VECTOR
83 config BOARD_ROMSIZE_KB_512
85 config BOARD_ROMSIZE_KB_1024
87 config BOARD_ROMSIZE_KB_2048
89 config BOARD_ROMSIZE_KB_4096
91 config BOARD_ROMSIZE_KB_8192
93 config BOARD_ROMSIZE_KB_16384
97 prompt "ROM chip size"
98 depends on X86_RESET_VECTOR
99 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
100 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
101 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
102 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
103 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
104 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
106 Select the size of the ROM chip you intend to flash U-Boot on.
108 The build system will take care of creating a u-boot.rom file
109 of the matching size.
111 config UBOOT_ROMSIZE_KB_512
114 Choose this option if you have a 512 KB ROM chip.
116 config UBOOT_ROMSIZE_KB_1024
117 bool "1024 KB (1 MB)"
119 Choose this option if you have a 1024 KB (1 MB) ROM chip.
121 config UBOOT_ROMSIZE_KB_2048
122 bool "2048 KB (2 MB)"
124 Choose this option if you have a 2048 KB (2 MB) ROM chip.
126 config UBOOT_ROMSIZE_KB_4096
127 bool "4096 KB (4 MB)"
129 Choose this option if you have a 4096 KB (4 MB) ROM chip.
131 config UBOOT_ROMSIZE_KB_8192
132 bool "8192 KB (8 MB)"
134 Choose this option if you have a 8192 KB (8 MB) ROM chip.
136 config UBOOT_ROMSIZE_KB_16384
137 bool "16384 KB (16 MB)"
139 Choose this option if you have a 16384 KB (16 MB) ROM chip.
143 # Map the config names to an integer (KB).
144 config UBOOT_ROMSIZE_KB
146 default 512 if UBOOT_ROMSIZE_KB_512
147 default 1024 if UBOOT_ROMSIZE_KB_1024
148 default 2048 if UBOOT_ROMSIZE_KB_2048
149 default 4096 if UBOOT_ROMSIZE_KB_4096
150 default 8192 if UBOOT_ROMSIZE_KB_8192
151 default 16384 if UBOOT_ROMSIZE_KB_16384
153 # Map the config names to a hex value (bytes).
156 default 0x80000 if UBOOT_ROMSIZE_KB_512
157 default 0x100000 if UBOOT_ROMSIZE_KB_1024
158 default 0x200000 if UBOOT_ROMSIZE_KB_2048
159 default 0x400000 if UBOOT_ROMSIZE_KB_4096
160 default 0x800000 if UBOOT_ROMSIZE_KB_8192
161 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
162 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
165 bool "Platform requires Intel Management Engine"
167 Newer higher-end devices have an Intel Management Engine (ME)
168 which is a very large binary blob (typically 1.5MB) which is
169 required for the platform to work. This enforces a particular
170 SPI flash format. You will need to supply the me.bin file in
171 your board directory.
174 bool "Perform a simple RAM test after SDRAM initialisation"
176 If there is something wrong with SDRAM then the platform will
177 often crash within U-Boot or the kernel. This option enables a
178 very simple RAM test that quickly checks whether the SDRAM seems
179 to work correctly. It is not exhaustive but can save time by
180 detecting obvious failures.
182 config MARK_GRAPHICS_MEM_WRCOMB
183 bool "Mark graphics memory as write-combining"
186 The graphics performance may increase if the graphics
187 memory is set as write-combining cache type. This option
188 enables marking the graphics memory as write-combining.
191 bool "Add an Firmware Support Package binary"
193 Select this option to add an Firmware Support Package binary to
194 the resulting U-Boot image. It is a binary blob which U-Boot uses
195 to set up SDRAM and other chipset specific initialization.
197 Note: Without this binary U-Boot will not be able to set up its
198 SDRAM so will not boot.
201 string "Firmware Support Package binary filename"
205 The filename of the file to use as Firmware Support Package binary
206 in the board directory.
209 hex "Firmware Support Package binary location"
213 FSP is not Position Independent Code (PIC) and the whole FSP has to
214 be rebased if it is placed at a location which is different from the
215 perferred base address specified during the FSP build. Use Intel's
216 Binary Configuration Tool (BCT) to do the rebase.
218 The default base address of 0xfffc0000 indicates that the binary must
219 be located at offset 0xc0000 from the beginning of a 1MB flash device.
221 config FSP_TEMP_RAM_ADDR
226 Stack top address which is used in FspInit after DRAM is ready and
230 int "Maximum number of CPUs permitted"
233 When using multi-CPU chips it is possible for U-Boot to start up
234 more than one CPU. The stack memory used by all of these CPUs is
235 pre-allocated so at present U-Boot wants to know the maximum
236 number of CPUs that may be present. Set this to at least as high
237 as the number of CPUs in your system (it uses about 4KB of RAM for
241 bool "Enable Symmetric Multiprocessing"
244 Enable use of more than one CPU in U-Boot and the Operating System
245 when loaded. Each CPU will be started up and information can be
246 obtained using the 'cpu' command. If this option is disabled, then
247 only one CPU will be enabled regardless of the number of CPUs
254 Each additional CPU started by U-Boot requires its own stack. This
255 option sets the stack size used by each CPU and directly affects
256 the memory used by this initialisation process. Typically 4KB is
259 config TSC_CALIBRATION_BYPASS
260 bool "Bypass Time-Stamp Counter (TSC) calibration"
263 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
264 running frequency via Model-Specific Register (MSR) and Programmable
265 Interval Timer (PIT). If the calibration does not work on your board,
266 select this option and provide a hardcoded TSC running frequency with
267 CONFIG_TSC_FREQ_IN_MHZ below.
269 Normally this option should be turned on in a simulation environment
272 config TSC_FREQ_IN_MHZ
273 int "Time-Stamp Counter (TSC) running frequency in MHz"
274 depends on TSC_CALIBRATION_BYPASS
277 The running frequency in MHz of Time-Stamp Counter (TSC).
281 config GENERATE_PIRQ_TABLE
282 bool "Generate a PIRQ table"
285 Generate a PIRQ routing table for this board. The PIRQ routing table
286 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
287 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
288 It specifies the interrupt router information as well how all the PCI
289 devices' interrupt pins are wired to PIRQs.
291 config GENERATE_SFI_TABLE
292 bool "Generate a SFI (Simple Firmware Interface) table"
294 The Simple Firmware Interface (SFI) provides a lightweight method
295 for platform firmware to pass information to the operating system
296 via static tables in memory. Kernel SFI support is required to
297 boot on SFI-only platforms. If you have ACPI tables then these are
300 U-Boot writes this table in write_sfi_table() just before booting
303 For more information, see http://simplefirmware.org
307 config MAX_PIRQ_LINKS
311 This variable specifies the number of PIRQ interrupt links which are
312 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
313 Some newer chipsets offer more than four links, commonly up to PIRQH.
315 config IRQ_SLOT_COUNT
319 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
320 which in turns forms a table of exact 4KiB. The default value 128
321 should be enough for most boards. If this does not fit your board,
322 change it according to your needs.
324 config PCIE_ECAM_BASE
328 This is the memory-mapped address of PCI configuration space, which
329 is only available through the Enhanced Configuration Access
330 Mechanism (ECAM) with PCI Express. It can be set up almost
331 anywhere. Before it is set up, it is possible to access PCI
332 configuration space through I/O access, but memory access is more
333 convenient. Using this, PCI can be scanned and configured. This
334 should be set to a region that does not conflict with memory
335 assigned to PCI devices - i.e. the memory and prefetch regions, as
336 passed to pci_set_region().
341 config BOOTSTAGE_REPORT