git.sur5r.net Git - u-boot/blob - arch/x86/cpu/baytrail/acpi.c

   1 /*
   2  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cpu.h>
   9 #include <dm.h>
  10 #include <dm/uclass-internal.h>
  11 #include <asm/acpi_s3.h>
  12 #include <asm/acpi_table.h>
  13 #include <asm/io.h>
  14 #include <asm/ioapic.h>
  15 #include <asm/mpspec.h>
  16 #include <asm/tables.h>
  17 #include <asm/arch/global_nvs.h>
  18 #include <asm/arch/iomap.h>
  19
  20 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
  21                       void *dsdt)
  22 {
  23         struct acpi_table_header *header = &(fadt->header);
  24         u16 pmbase = ACPI_BASE_ADDRESS;
  25
  26         memset((void *)fadt, 0, sizeof(struct acpi_fadt));
  27
  28         acpi_fill_header(header, "FACP");
  29         header->length = sizeof(struct acpi_fadt);
  30         header->revision = 4;
  31
  32         fadt->firmware_ctrl = (u32)facs;
  33         fadt->dsdt = (u32)dsdt;
  34         fadt->preferred_pm_profile = ACPI_PM_MOBILE;
  35         fadt->sci_int = 9;
  36         fadt->smi_cmd = 0;
  37         fadt->acpi_enable = 0;
  38         fadt->acpi_disable = 0;
  39         fadt->s4bios_req = 0;
  40         fadt->pstate_cnt = 0;
  41         fadt->pm1a_evt_blk = pmbase;
  42         fadt->pm1b_evt_blk = 0x0;
  43         fadt->pm1a_cnt_blk = pmbase + 0x4;
  44         fadt->pm1b_cnt_blk = 0x0;
  45         fadt->pm2_cnt_blk = pmbase + 0x50;
  46         fadt->pm_tmr_blk = pmbase + 0x8;
  47         fadt->gpe0_blk = pmbase + 0x20;
  48         fadt->gpe1_blk = 0;
  49         fadt->pm1_evt_len = 4;
  50         fadt->pm1_cnt_len = 2;
  51         fadt->pm2_cnt_len = 1;
  52         fadt->pm_tmr_len = 4;
  53         fadt->gpe0_blk_len = 8;
  54         fadt->gpe1_blk_len = 0;
  55         fadt->gpe1_base = 0;
  56         fadt->cst_cnt = 0;
  57         fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
  58         fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
  59         fadt->flush_size = 0;
  60         fadt->flush_stride = 0;
  61         fadt->duty_offset = 1;
  62         fadt->duty_width = 0;
  63         fadt->day_alrm = 0x0d;
  64         fadt->mon_alrm = 0x00;
  65         fadt->century = 0x00;
  66         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
  67         fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
  68                 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
  69                 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
  70                 ACPI_FADT_PLATFORM_CLOCK;
  71
  72         fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
  73         fadt->reset_reg.bit_width = 8;
  74         fadt->reset_reg.bit_offset = 0;
  75         fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
  76         fadt->reset_reg.addrl = IO_PORT_RESET;
  77         fadt->reset_reg.addrh = 0;
  78         fadt->reset_value = SYS_RST | RST_CPU;
  79
  80         fadt->x_firmware_ctl_l = (u32)facs;
  81         fadt->x_firmware_ctl_h = 0;
  82         fadt->x_dsdt_l = (u32)dsdt;
  83         fadt->x_dsdt_h = 0;
  84
  85         fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  86         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  87         fadt->x_pm1a_evt_blk.bit_offset = 0;
  88         fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
  89         fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
  90         fadt->x_pm1a_evt_blk.addrh = 0x0;
  91
  92         fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  93         fadt->x_pm1b_evt_blk.bit_width = 0;
  94         fadt->x_pm1b_evt_blk.bit_offset = 0;
  95         fadt->x_pm1b_evt_blk.access_size = 0;
  96         fadt->x_pm1b_evt_blk.addrl = 0x0;
  97         fadt->x_pm1b_evt_blk.addrh = 0x0;
  98
  99         fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 100         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
 101         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 102         fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 103         fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
 104         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 105
 106         fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 107         fadt->x_pm1b_cnt_blk.bit_width = 0;
 108         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 109         fadt->x_pm1b_cnt_blk.access_size = 0;
 110         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 111         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 112
 113         fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 114         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 115         fadt->x_pm2_cnt_blk.bit_offset = 0;
 116         fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 117         fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
 118         fadt->x_pm2_cnt_blk.addrh = 0x0;
 119
 120         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 121         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 122         fadt->x_pm_tmr_blk.bit_offset = 0;
 123         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 124         fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
 125         fadt->x_pm_tmr_blk.addrh = 0x0;
 126
 127         fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 128         fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
 129         fadt->x_gpe0_blk.bit_offset = 0;
 130         fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 131         fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
 132         fadt->x_gpe0_blk.addrh = 0x0;
 133
 134         fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 135         fadt->x_gpe1_blk.bit_width = 0;
 136         fadt->x_gpe1_blk.bit_offset = 0;
 137         fadt->x_gpe1_blk.access_size = 0;
 138         fadt->x_gpe1_blk.addrl = 0x0;
 139         fadt->x_gpe1_blk.addrh = 0x0;
 140
 141         header->checksum = table_compute_checksum(fadt, header->length);
 142 }
 143
 144 static int acpi_create_madt_irq_overrides(u32 current)
 145 {
 146         struct acpi_madt_irqoverride *irqovr;
 147         u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
 148         int length = 0;
 149
 150         irqovr = (void *)current;
 151         length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
 152
 153         irqovr = (void *)(current + length);
 154         length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
 155
 156         return length;
 157 }
 158
 159 u32 acpi_fill_madt(u32 current)
 160 {
 161         current += acpi_create_madt_lapics(current);
 162
 163         current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
 164                         io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
 165
 166         current += acpi_create_madt_irq_overrides(current);
 167
 168         return current;
 169 }
 170
 171 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 172 {
 173         struct udevice *dev;
 174         int ret;
 175
 176         /* at least we have one processor */
 177         gnvs->pcnt = 1;
 178         /* override the processor count with actual number */
 179         ret = uclass_find_first_device(UCLASS_CPU, &dev);
 180         if (ret == 0 && dev != NULL) {
 181                 ret = cpu_get_count(dev);
 182                 if (ret > 0)
 183                         gnvs->pcnt = ret;
 184         }
 185
 186         /* determine whether internal uart is on */
 187         if (IS_ENABLED(CONFIG_INTERNAL_UART))
 188                 gnvs->iuart_en = 1;
 189         else
 190                 gnvs->iuart_en = 0;
 191 }
 192
 193 #ifdef CONFIG_HAVE_ACPI_RESUME
 194 /*
 195  * The following two routines are called at a very early stage, even before
 196  * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
 197  * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
 198  * of these two blocks are programmed by either U-Boot or FSP.
 199  *
 200  * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S)
 201  * on Intel BayTrail SoC already initializes these two base addresses so
 202  * we are safe to access these registers here.
 203  */
 204
 205 enum acpi_sleep_state chipset_prev_sleep_state(void)
 206 {
 207         u32 pm1_sts;
 208         u32 pm1_cnt;
 209         u32 gen_pmcon1;
 210         enum acpi_sleep_state prev_sleep_state = ACPI_S0;
 211
 212         /* Read Power State */
 213         pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 214         pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 215         gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
 216
 217         debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
 218               pm1_sts, pm1_cnt, gen_pmcon1);
 219
 220         if (pm1_sts & WAK_STS)
 221                 prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
 222
 223         if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
 224                 prev_sleep_state = ACPI_S5;
 225
 226         return prev_sleep_state;
 227 }
 228
 229 void chipset_clear_sleep_state(void)
 230 {
 231         u32 pm1_cnt;
 232
 233         pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 234         outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
 235 }
 236 #endif