2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
6 * Based on code from coreboot src/soc/intel/broadwell/me_status.c
11 #include <asm/arch/me.h>
13 static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
17 dm_pci_read_config32(dev, offset, &dword);
18 memcpy(ptr, &dword, sizeof(dword));
21 int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
28 /* Query for HSIO version, overloads H_GS and HFS */
29 dm_pci_write_config32(dev, PCI_ME_H_GS,
30 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
32 /* Must wait for ME acknowledgement */
33 for (count = ME_RETRY; count > 0; --count) {
34 me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
40 debug("ERROR: ME failed to respond\n");
44 /* HSIO version should be in HFS_5 */
45 dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
46 *versionp = hsiover >> 16;
47 *checksump = hsiover & 0xffff;
49 debug("ME: HSIO Version : %d (CRC 0x%04x)\n",
50 *versionp, *checksump);
52 /* Reset registers to normal behavior */
53 dm_pci_write_config32(dev, PCI_ME_H_GS,
54 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);