2 * Copyright (C) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/gpio.h>
18 #include <dt-bindings/gpio/x86-gpio.h>
19 #include <dm/pinctrl.h>
21 DECLARE_GLOBAL_DATA_PTR;
28 #define CONF_MASK 0xffff
46 static int broadwell_pinctrl_read_configs(struct udevice *dev,
47 struct pin_info *conf, int max_pins)
49 const void *blob = gd->fdt_blob;
53 debug("%s: starting\n", __func__);
54 for (node = fdt_first_subnode(blob, dev->of_offset);
56 node = fdt_next_subnode(blob, node)) {
57 int phandle = fdt_get_phandle(blob, node);
61 if (count == max_pins)
64 /* We've found a new configuration */
65 memset(conf, '\0', sizeof(*conf));
67 conf->phandle = phandle;
68 conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
69 if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
70 conf->dir_input = true;
71 conf->invert = fdtdec_get_bool(blob, node, "invert");
72 if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
73 conf->trigger_level = true;
74 if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
75 conf->output_high = true;
76 conf->sense_disable = fdtdec_get_bool(blob, node,
78 if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
79 conf->owner_gpio = true;
80 if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
81 conf->route_smi = true;
82 conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
83 conf->reset_rsmrst = fdtdec_get_bool(blob, node,
85 if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
87 conf->pirq_apic_route = true;
88 debug("config: phandle=%d\n", phandle);
92 debug("%s: Found %d configurations\n", __func__, count);
97 static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
98 int conf_count, int phandle)
102 for (i = 0; i < conf_count; i++) {
103 if (conf[i].phandle == phandle)
110 static int broadwell_pinctrl_read_pins(struct udevice *dev,
111 struct pin_info *conf, int conf_count, int gpio_conf[],
114 const void *blob = gd->fdt_blob;
118 for (node = fdt_first_subnode(blob, dev->of_offset);
120 node = fdt_next_subnode(blob, node)) {
122 const u32 *prop = fdt_getprop(blob, node, "config", &len);
127 /* There are three cells per pin */
128 count = len / (sizeof(u32) * 3);
129 debug("Found %d GPIOs to configure\n", count);
130 for (i = 0; i < count; i++) {
131 uint gpio = fdt32_to_cpu(prop[i * 3]);
132 uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
135 if (gpio >= num_gpios) {
136 debug("%s: GPIO %d out of range\n", __func__,
140 val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
143 debug("%s: Cannot find phandle %d\n", __func__,
147 gpio_conf[gpio] = val |
148 fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
155 static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
156 struct pin_info *pin_info,
157 int gpio_conf[], int count)
159 u32 owner_gpio[GPIO_BANKS] = {0};
160 u32 route_smi[GPIO_BANKS] = {0};
161 u32 irq_enable[GPIO_BANKS] = {0};
162 u32 reset_rsmrst[GPIO_BANKS] = {0};
164 int set, bit, gpio = 0;
166 for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
167 int confnum = gpio_conf[gpio] & CONF_MASK;
168 struct pin_info *pin = &pin_info[confnum];
171 val = pin->mode_gpio << CONFA_MODE_SHIFT |
172 pin->dir_input << CONFA_DIR_SHIFT |
173 pin->invert << CONFA_INVERT_SHIFT |
174 pin->trigger_level << CONFA_TRIGGER_SHIFT |
175 pin->output_high << CONFA_OUTPUT_SHIFT;
176 outl(val, ®s->config[gpio].conf_a);
177 outl(pin->sense_disable << CONFB_SENSE_SHIFT,
178 ®s->config[gpio].conf_b);
180 /* Determine set and bit based on GPIO number */
181 set = gpio / GPIO_PER_BANK;
182 bit = gpio % GPIO_PER_BANK;
184 /* Apply settings to set specific bits */
185 owner_gpio[set] |= pin->owner_gpio << bit;
186 route_smi[set] |= pin->route_smi << bit;
187 irq_enable[set] |= pin->irq_enable << bit;
188 reset_rsmrst[set] |= pin->reset_rsmrst << bit;
190 /* PIRQ to IO-APIC map */
191 if (pin->pirq_apic_route)
192 pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
193 debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
194 gpio, confnum, pin->mode_gpio, pin->dir_input,
198 for (set = 0; set < GPIO_BANKS; set++) {
199 outl(owner_gpio[set], ®s->own[set]);
200 outl(route_smi[set], ®s->gpi_route[set]);
201 outl(irq_enable[set], ®s->gpi_ie[set]);
202 outl(reset_rsmrst[set], ®s->rst_sel[set]);
205 outl(pirq2apic, ®s->pirq_to_ioxapic);
208 static int broadwell_pinctrl_probe(struct udevice *dev)
210 struct pch_lp_gpio_regs *regs;
211 struct pin_info conf[12];
212 int gpio_conf[MAX_GPIOS];
218 ret = uclass_first_device(UCLASS_PCH, &pch);
223 debug("%s: start\n", __func__);
225 /* Only init once, before relocation */
226 if (gd->flags & GD_FLG_RELOC)
230 * Get the memory/io base address to configure every pins.
231 * IOBASE is used to configure the mode/pads
232 * GPIOBASE is used to configure the direction and default value
234 ret = pch_get_gpio_base(pch, &gpiobase);
236 debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
241 conf_count = broadwell_pinctrl_read_configs(dev, conf,
243 if (conf_count < 0) {
244 debug("%s: Cannot read configs: err=%d\n", __func__, ret);
249 * Assume that pin settings are provided for every pin. Pins not
250 * mentioned will get the first config mentioned in the list.
252 ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
255 debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
259 regs = (struct pch_lp_gpio_regs *)gpiobase;
260 broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
262 debug("%s: done\n", __func__);
267 static const struct udevice_id broadwell_pinctrl_match[] = {
268 { .compatible = "intel,x86-broadwell-pinctrl",
269 .data = X86_SYSCON_PINCONF },
273 U_BOOT_DRIVER(broadwell_pinctrl) = {
274 .name = "broadwell_pinctrl",
276 .of_match = broadwell_pinctrl_match,
277 .probe = broadwell_pinctrl_probe,