1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * Graeme Russ, graeme.russ@gmail.com.
13 #include <asm/arch/sysinfo.h>
14 #include <asm/arch/timestamp.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 int arch_cpu_init(void)
20 int ret = get_coreboot_info(&lib_sysinfo);
22 printf("Failed to parse coreboot tables.\n");
28 return x86_cpu_init_f();
36 int print_cpuinfo(void)
38 return default_print_cpuinfo();
41 static void board_final_cleanup(void)
44 * Un-cache the ROM so the kernel has one
45 * more MTRR available.
47 * Coreboot should have assigned this to the
48 * top available variable MTRR.
50 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
51 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
53 /* Make sure this MTRR is the correct Write-Protected type */
54 if (top_type == MTRR_TYPE_WRPROT) {
55 struct mtrr_state state;
58 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
59 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
63 if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
65 * Issue SMI to coreboot to lock down ME and registers
66 * when allowed via device tree
68 printf("Finalizing coreboot\n");
73 int last_stage_init(void)
75 if (gd->flags & GD_FLG_COLD_BOOT)
76 timestamp_add_to_bootstage();
78 board_final_cleanup();