2 * Copyright (c) 2011 The Chromium OS Authors.
4 * Graeme Russ, graeme.russ@gmail.com.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/u-boot-x86.h>
30 #include <asm/cache.h>
32 #include <asm/arch-coreboot/tables.h>
33 #include <asm/arch-coreboot/sysinfo.h>
34 #include <asm/arch/timestamp.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
41 * Miscellaneous platform dependent initializations
45 int ret = get_coreboot_info(&lib_sysinfo);
47 printf("Failed to parse coreboot tables.\n");
54 int board_early_init_f(void)
59 int board_early_init_r(void)
61 /* CPU Speed to 100MHz */
62 gd->cpu_clk = 100000000;
64 /* Crystal is 33.000MHz */
65 gd->bus_clk = 33000000;
70 void show_boot_progress(int val)
72 #if MIN_PORT80_KCLOCKS_DELAY
73 static uint32_t prev_stamp;
77 * Scale the time counter reading to avoid using 64 bit arithmetics.
78 * Can't use get_timer() here becuase it could be not yet
79 * initialized or even implemented.
82 base = rdtsc() / 1000;
88 now = rdtsc() / 1000 - base;
89 } while (now < (prev_stamp + MIN_PORT80_KCLOCKS_DELAY));
97 int last_stage_init(void)
102 #ifndef CONFIG_SYS_NO_FLASH
103 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
109 int board_eth_init(bd_t *bis)
111 return pci_eth_init(bis);
114 void setup_pcat_compatibility()
118 #define MTRR_TYPE_WP 5
119 #define MTRRcap_MSR 0xfe
120 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
121 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
123 int board_final_cleanup(void)
125 /* Un-cache the ROM so the kernel has one
126 * more MTRR available.
128 * Coreboot should have assigned this to the
129 * top available variable MTRR.
131 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
132 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
134 /* Make sure this MTRR is the correct Write-Protected type */
135 if (top_type == MTRR_TYPE_WP) {
137 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
138 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
142 /* Issue SMI to Coreboot to lock down ME and registers */
143 printf("Finalizing Coreboot\n");