git.sur5r.net Git - u-boot/blob - arch/x86/cpu/coreboot/coreboot.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008
   4  * Graeme Russ, graeme.russ@gmail.com.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <fdtdec.h>
  11 #include <asm/io.h>
  12 #include <asm/msr.h>
  13 #include <asm/mtrr.h>
  14 #include <asm/arch/sysinfo.h>
  15 #include <asm/arch/timestamp.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int arch_cpu_init(void)
  20 {
  21         int ret = get_coreboot_info(&lib_sysinfo);
  22         if (ret != 0) {
  23                 printf("Failed to parse coreboot tables.\n");
  24                 return ret;
  25         }
  26
  27         timestamp_init();
  28
  29         return x86_cpu_init_f();
  30 }
  31
  32 int board_early_init_f(void)
  33 {
  34         return 0;
  35 }
  36
  37 int print_cpuinfo(void)
  38 {
  39         return default_print_cpuinfo();
  40 }
  41
  42 static void board_final_cleanup(void)
  43 {
  44         /*
  45          * Un-cache the ROM so the kernel has one
  46          * more MTRR available.
  47          *
  48          * Coreboot should have assigned this to the
  49          * top available variable MTRR.
  50          */
  51         u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
  52         u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
  53
  54         /* Make sure this MTRR is the correct Write-Protected type */
  55         if (top_type == MTRR_TYPE_WRPROT) {
  56                 struct mtrr_state state;
  57
  58                 mtrr_open(&state);
  59                 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
  60                 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
  61                 mtrr_close(&state);
  62         }
  63
  64         if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
  65                 /*
  66                  * Issue SMI to coreboot to lock down ME and registers
  67                  * when allowed via device tree
  68                  */
  69                 printf("Finalizing coreboot\n");
  70                 outb(0xcb, 0xb2);
  71         }
  72 }
  73
  74 int last_stage_init(void)
  75 {
  76         if (gd->flags & GD_FLG_COLD_BOOT)
  77                 timestamp_add_to_bootstage();
  78
  79         board_final_cleanup();
  80
  81         return 0;
  82 }
  83
  84 int misc_init_r(void)
  85 {
  86         return 0;
  87 }
  88
  89 int arch_misc_init(void)
  90 {
  91         return 0;
  92 }