git.sur5r.net Git - u-boot/blob - arch/x86/cpu/coreboot/pci.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008,2009
   4  * Graeme Russ, <graeme.russ@gmail.com>
   5  *
   6  * (C) Copyright 2002
   7  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <pci.h>
  14 #include <asm/pci.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
  19                               struct pci_config_table *table)
  20 {
  21         u8 secondary;
  22         hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
  23         hose->last_busno = max(hose->last_busno, (int)secondary);
  24         pci_hose_scan_bus(hose, secondary);
  25 }
  26
  27 static struct pci_config_table pci_coreboot_config_table[] = {
  28         /* vendor, device, class, bus, dev, func */
  29         { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
  30                 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
  31         {}
  32 };
  33
  34 void board_pci_setup_hose(struct pci_controller *hose)
  35 {
  36         hose->config_table = pci_coreboot_config_table;
  37         hose->first_busno = 0;
  38         hose->last_busno = 0;
  39
  40         /* PCI memory space */
  41         pci_set_region(hose->regions + 0,
  42                        CONFIG_PCI_MEM_BUS,
  43                        CONFIG_PCI_MEM_PHYS,
  44                        CONFIG_PCI_MEM_SIZE,
  45                        PCI_REGION_MEM);
  46
  47         /* PCI IO space */
  48         pci_set_region(hose->regions + 1,
  49                        CONFIG_PCI_IO_BUS,
  50                        CONFIG_PCI_IO_PHYS,
  51                        CONFIG_PCI_IO_SIZE,
  52                        PCI_REGION_IO);
  53
  54         pci_set_region(hose->regions + 2,
  55                        CONFIG_PCI_PREF_BUS,
  56                        CONFIG_PCI_PREF_PHYS,
  57                        CONFIG_PCI_PREF_SIZE,
  58                        PCI_REGION_PREFETCH);
  59
  60         pci_set_region(hose->regions + 3,
  61                        0,
  62                        0,
  63                        gd->ram_size,
  64                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  65
  66         hose->region_count = 4;
  67 }