2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
16 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
19 * SPDX-License-Identifier: GPL-2.0+
28 #include <asm/control_regs.h>
31 #include <asm/processor.h>
32 #include <asm/processor-flags.h>
33 #include <asm/interrupt.h>
34 #include <asm/tables.h>
35 #include <linux/compiler.h>
37 DECLARE_GLOBAL_DATA_PTR;
40 * Constructor for a conventional segment GDT (or LDT) entry
41 * This is a macro so it can be used in initialisers
43 #define GDT_ENTRY(flags, base, limit) \
44 ((((base) & 0xff000000ULL) << (56-24)) | \
45 (((flags) & 0x0000f0ffULL) << 40) | \
46 (((limit) & 0x000f0000ULL) << (48-16)) | \
47 (((base) & 0x00ffffffULL) << 16) | \
48 (((limit) & 0x0000ffffULL)))
55 struct cpu_device_id {
61 uint8_t x86; /* CPU family */
62 uint8_t x86_vendor; /* CPU vendor */
68 * List of cpu vendor strings along with their normalized
75 { X86_VENDOR_INTEL, "GenuineIntel", },
76 { X86_VENDOR_CYRIX, "CyrixInstead", },
77 { X86_VENDOR_AMD, "AuthenticAMD", },
78 { X86_VENDOR_UMC, "UMC UMC UMC ", },
79 { X86_VENDOR_NEXGEN, "NexGenDriven", },
80 { X86_VENDOR_CENTAUR, "CentaurHauls", },
81 { X86_VENDOR_RISE, "RiseRiseRise", },
82 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
83 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
84 { X86_VENDOR_NSC, "Geode by NSC", },
85 { X86_VENDOR_SIS, "SiS SiS SiS ", },
88 static const char *const x86_vendor_name[] = {
89 [X86_VENDOR_INTEL] = "Intel",
90 [X86_VENDOR_CYRIX] = "Cyrix",
91 [X86_VENDOR_AMD] = "AMD",
92 [X86_VENDOR_UMC] = "UMC",
93 [X86_VENDOR_NEXGEN] = "NexGen",
94 [X86_VENDOR_CENTAUR] = "Centaur",
95 [X86_VENDOR_RISE] = "Rise",
96 [X86_VENDOR_TRANSMETA] = "Transmeta",
97 [X86_VENDOR_NSC] = "NSC",
98 [X86_VENDOR_SIS] = "SiS",
101 static void load_ds(u32 segment)
103 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
106 static void load_es(u32 segment)
108 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
111 static void load_fs(u32 segment)
113 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
116 static void load_gs(u32 segment)
118 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
121 static void load_ss(u32 segment)
123 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
126 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
130 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
131 gdt.ptr = (u32)boot_gdt;
133 asm volatile("lgdtl %0\n" : : "m" (gdt));
136 void setup_gdt(gd_t *id, u64 *gdt_addr)
138 id->arch.gdt = gdt_addr;
139 /* CS: code, read/execute, 4 GB, base 0 */
140 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
142 /* DS: data, read/write, 4 GB, base 0 */
143 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
145 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
146 id->arch.gd_addr = id;
147 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
148 (ulong)&id->arch.gd_addr, 0xfffff);
150 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
151 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
153 /* 16-bit DS: data, read/write, 64 kB, base 0 */
154 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
156 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
157 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
159 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
160 load_ds(X86_GDT_ENTRY_32BIT_DS);
161 load_es(X86_GDT_ENTRY_32BIT_DS);
162 load_gs(X86_GDT_ENTRY_32BIT_DS);
163 load_ss(X86_GDT_ENTRY_32BIT_DS);
164 load_fs(X86_GDT_ENTRY_32BIT_FS);
167 int __weak x86_cleanup_before_linux(void)
169 #ifdef CONFIG_BOOTSTAGE_STASH
170 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
171 CONFIG_BOOTSTAGE_STASH_SIZE);
178 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
179 * by the fact that they preserve the flags across the division of 5/2.
180 * PII and PPro exhibit this behavior too, but they have cpuid available.
184 * Perform the Cyrix 5/2 test. A Cyrix won't change
185 * the flags, while other 486 chips will.
187 static inline int test_cyrix_52div(void)
191 __asm__ __volatile__(
192 "sahf\n\t" /* clear flags (%eax = 0x0005) */
193 "div %b2\n\t" /* divide 5 by 2 */
194 "lahf" /* store flags into %ah */
199 /* AH is 0x02 on Cyrix after the divide.. */
200 return (unsigned char) (test >> 8) == 0x02;
204 * Detect a NexGen CPU running without BIOS hypercode new enough
205 * to have CPUID. (Thanks to Herbert Oppmann)
208 static int deep_magic_nexgen_probe(void)
212 __asm__ __volatile__ (
213 " movw $0x5555, %%ax\n"
221 : "=a" (ret) : : "cx", "dx");
225 static bool has_cpuid(void)
227 return flag_is_changeable_p(X86_EFLAGS_ID);
230 static bool has_mtrr(void)
232 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
235 static int build_vendor_name(char *vendor_name)
237 struct cpuid_result result;
238 result = cpuid(0x00000000);
239 unsigned int *name_as_ints = (unsigned int *)vendor_name;
241 name_as_ints[0] = result.ebx;
242 name_as_ints[1] = result.edx;
243 name_as_ints[2] = result.ecx;
248 static void identify_cpu(struct cpu_device_id *cpu)
250 char vendor_name[16];
253 vendor_name[0] = '\0'; /* Unset */
254 cpu->device = 0; /* fix gcc 4.4.4 warning */
256 /* Find the id and vendor_name */
258 /* Its a 486 if we can modify the AC flag */
259 if (flag_is_changeable_p(X86_EFLAGS_AC))
260 cpu->device = 0x00000400; /* 486 */
262 cpu->device = 0x00000300; /* 386 */
263 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
264 memcpy(vendor_name, "CyrixInstead", 13);
265 /* If we ever care we can enable cpuid here */
267 /* Detect NexGen with old hypercode */
268 else if (deep_magic_nexgen_probe())
269 memcpy(vendor_name, "NexGenDriven", 13);
274 cpuid_level = build_vendor_name(vendor_name);
275 vendor_name[12] = '\0';
277 /* Intel-defined flags: level 0x00000001 */
278 if (cpuid_level >= 0x00000001) {
279 cpu->device = cpuid_eax(0x00000001);
281 /* Have CPUID level 0 only unheard of */
282 cpu->device = 0x00000400;
285 cpu->vendor = X86_VENDOR_UNKNOWN;
286 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
287 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
288 cpu->vendor = x86_vendors[i].vendor;
294 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
296 c->x86 = (tfms >> 8) & 0xf;
297 c->x86_model = (tfms >> 4) & 0xf;
298 c->x86_mask = tfms & 0xf;
300 c->x86 += (tfms >> 20) & 0xff;
302 c->x86_model += ((tfms >> 16) & 0xF) << 4;
305 int x86_cpu_init_f(void)
307 const u32 em_rst = ~X86_CR0_EM;
308 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
310 /* initialize FPU, reset EM, set MP and NE */
312 "movl %%cr0, %%eax\n" \
315 "movl %%eax, %%cr0\n" \
316 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
318 /* identify CPU via cpuid and store the decoded info into gd->arch */
320 struct cpu_device_id cpu;
321 struct cpuinfo_x86 c;
324 get_fms(&c, cpu.device);
325 gd->arch.x86 = c.x86;
326 gd->arch.x86_vendor = cpu.vendor;
327 gd->arch.x86_model = c.x86_model;
328 gd->arch.x86_mask = c.x86_mask;
329 gd->arch.x86_device = cpu.device;
331 gd->arch.has_mtrr = has_mtrr();
337 void x86_enable_caches(void)
342 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
346 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
348 void x86_disable_caches(void)
353 cr0 |= X86_CR0_NW | X86_CR0_CD;
358 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
360 int x86_init_cache(void)
366 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
368 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
370 printf("resetting ...\n");
374 disable_interrupts();
381 void flush_cache(unsigned long dummy1, unsigned long dummy2)
386 __weak void reset_cpu(ulong addr)
388 /* Do a hard reset through the chipset's reset control register */
389 outb(SYS_RST | RST_CPU, PORT_RESET);
394 void x86_full_reset(void)
396 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
399 int dcache_status(void)
401 return !(read_cr0() & 0x40000000);
404 /* Define these functions to allow ehch-hcd to function */
405 void flush_dcache_range(unsigned long start, unsigned long stop)
409 void invalidate_dcache_range(unsigned long start, unsigned long stop)
413 void dcache_enable(void)
418 void dcache_disable(void)
423 void icache_enable(void)
427 void icache_disable(void)
431 int icache_status(void)
436 void cpu_enable_paging_pae(ulong cr3)
438 __asm__ __volatile__(
439 /* Load the page table address */
442 "movl %%cr4, %%eax\n"
443 "orl $0x00000020, %%eax\n"
444 "movl %%eax, %%cr4\n"
446 "movl %%cr0, %%eax\n"
447 "orl $0x80000000, %%eax\n"
448 "movl %%eax, %%cr0\n"
454 void cpu_disable_paging_pae(void)
456 /* Turn off paging */
457 __asm__ __volatile__ (
459 "movl %%cr0, %%eax\n"
460 "andl $0x7fffffff, %%eax\n"
461 "movl %%eax, %%cr0\n"
463 "movl %%cr4, %%eax\n"
464 "andl $0xffffffdf, %%eax\n"
465 "movl %%eax, %%cr4\n"
471 static bool can_detect_long_mode(void)
473 return cpuid_eax(0x80000000) > 0x80000000UL;
476 static bool has_long_mode(void)
478 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
481 int cpu_has_64bit(void)
483 return has_cpuid() && can_detect_long_mode() &&
487 const char *cpu_vendor_name(int vendor)
490 name = "<invalid cpu vendor>";
491 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
492 (x86_vendor_name[vendor] != 0))
493 name = x86_vendor_name[vendor];
498 char *cpu_get_name(char *name)
500 unsigned int *name_as_ints = (unsigned int *)name;
501 struct cpuid_result regs;
505 /* This bit adds up to 48 bytes */
506 for (i = 0; i < 3; i++) {
507 regs = cpuid(0x80000002 + i);
508 name_as_ints[i * 4 + 0] = regs.eax;
509 name_as_ints[i * 4 + 1] = regs.ebx;
510 name_as_ints[i * 4 + 2] = regs.ecx;
511 name_as_ints[i * 4 + 3] = regs.edx;
513 name[CPU_MAX_NAME_LEN - 1] = '\0';
515 /* Skip leading spaces. */
523 int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
525 if (size < CPU_MAX_NAME_LEN)
533 int default_print_cpuinfo(void)
535 printf("CPU: %s, vendor %s, device %xh\n",
536 cpu_has_64bit() ? "x86_64" : "x86",
537 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
542 #define PAGETABLE_SIZE (6 * 4096)
545 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
547 * @pgtable: Pointer to a 24iKB block of memory
549 static void build_pagetable(uint32_t *pgtable)
553 memset(pgtable, '\0', PAGETABLE_SIZE);
555 /* Level 4 needs a single entry */
556 pgtable[0] = (uint32_t)&pgtable[1024] + 7;
558 /* Level 3 has one 64-bit entry for each GiB of memory */
559 for (i = 0; i < 4; i++) {
560 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
564 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
565 for (i = 0; i < 2048; i++)
566 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
569 int cpu_jump_to_64bit(ulong setup_base, ulong target)
573 pgtable = memalign(4096, PAGETABLE_SIZE);
577 build_pagetable(pgtable);
578 cpu_call64((ulong)pgtable, setup_base, target);
584 void show_boot_progress(int val)
586 #if MIN_PORT80_KCLOCKS_DELAY
588 * Scale the time counter reading to avoid using 64 bit arithmetics.
589 * Can't use get_timer() here becuase it could be not yet
590 * initialized or even implemented.
592 if (!gd->arch.tsc_prev) {
593 gd->arch.tsc_base_kclocks = rdtsc() / 1000;
594 gd->arch.tsc_prev = 0;
599 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
600 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
601 gd->arch.tsc_prev = now;
604 outb(val, POST_PORT);
607 #ifndef CONFIG_SYS_COREBOOT
608 int last_stage_init(void)
616 __weak int x86_init_cpus(void)
623 return x86_init_cpus();
626 static const struct cpu_ops cpu_x86_ops = {
627 .get_desc = x86_cpu_get_desc,
630 static const struct udevice_id cpu_x86_ids[] = {
631 { .compatible = "cpu-x86" },
635 U_BOOT_DRIVER(cpu_x86_drv) = {
638 .of_match = cpu_x86_ids,