2 * Copyright (c) 2014 Google, Inc
3 * Copyright (C) 2000 Ronald G. Minnich
5 * Microcode update for Intel PIII and later CPUs
7 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/microcode.h>
17 #include <asm/msr-index.h>
18 #include <asm/processor.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 * struct microcode_update - standard microcode header from Intel
25 * We read this information out of the device tree and use it to determine
26 * whether the update is applicable or not. We also use the same structure
27 * to read information from the CPU.
29 struct microcode_update {
33 uint processor_signature;
41 static int microcode_decode_node(const void *blob, int node,
42 struct microcode_update *update)
44 update->data = fdt_getprop(blob, node, "data", &update->size);
47 update->data += UCODE_HEADER_LEN;
48 update->size -= UCODE_HEADER_LEN;
50 update->header_version = fdtdec_get_int(blob, node,
51 "intel,header-version", 0);
52 update->update_revision = fdtdec_get_int(blob, node,
53 "intel,update-revision", 0);
54 update->date_code = fdtdec_get_int(blob, node,
55 "intel,date-code", 0);
56 update->processor_signature = fdtdec_get_int(blob, node,
57 "intel,processor-signature", 0);
58 update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
59 update->loader_revision = fdtdec_get_int(blob, node,
60 "intel,loader-revision", 0);
61 update->processor_flags = fdtdec_get_int(blob, node,
62 "intel,processor-flags", 0);
67 int microcode_read_rev(void)
69 /* Quark does not have microcode MSRs */
70 #ifdef CONFIG_INTEL_QUARK
74 * Some Intel CPUs can be very finicky about the CPUID sequence used.
75 * So this is implemented in assembly so that it works reliably.
89 "=a" (low), "=d" (high)
91 "i" (MSR_IA32_UCODE_REV)
100 static void microcode_read_cpu(struct microcode_update *cpu)
102 /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
103 unsigned int x86_model, x86_family;
104 struct cpuid_result result;
107 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
109 rdmsr(MSR_IA32_UCODE_REV, low, cpu->update_revision);
110 x86_model = (result.eax >> 4) & 0x0f;
111 x86_family = (result.eax >> 8) & 0x0f;
112 cpu->processor_signature = result.eax;
114 cpu->processor_flags = 0;
115 if ((x86_model >= 5) || (x86_family > 6)) {
116 rdmsr(0x17, low, high);
117 cpu->processor_flags = 1 << ((high >> 18) & 7);
119 debug("microcode: sig=%#x pf=%#x revision=%#x\n",
120 cpu->processor_signature, cpu->processor_flags,
121 cpu->update_revision);
124 /* Get a microcode update from the device tree and apply it */
125 int microcode_update_intel(void)
127 struct microcode_update cpu, update;
128 const void *blob = gd->fdt_blob;
135 microcode_read_cpu(&cpu);
140 node = fdtdec_next_compatible(blob, node,
141 COMPAT_INTEL_MICROCODE);
143 debug("%s: Found %d updates\n", __func__, count);
144 return count ? 0 : skipped ? -EEXIST : -ENOENT;
147 ret = microcode_decode_node(blob, node, &update);
149 debug("%s: Unable to decode update: %d\n", __func__,
153 if (!(update.processor_signature == cpu.processor_signature &&
154 (update.processor_flags & cpu.processor_flags))) {
155 debug("%s: Skipping non-matching update, sig=%x, pf=%x\n",
156 __func__, update.processor_signature,
157 update.processor_flags);
161 wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0);
162 rev = microcode_read_rev();
163 debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
164 rev, update.date_code & 0xffff,
165 (update.date_code >> 24) & 0xff,
166 (update.date_code >> 16) & 0xff);
167 if (update.update_revision != rev) {
168 printf("Microcode update failed\n");