git.sur5r.net Git - u-boot/blob - arch/x86/cpu/irq.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <asm/irq.h>
  13 #include <asm/pci.h>
  14 #include <asm/pirq_routing.h>
  15 #include <asm/tables.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
  20 {
  21         struct irq_router *priv = dev_get_priv(dev);
  22         u8 pirq;
  23         int base = priv->link_base;
  24
  25         if (priv->config == PIRQ_VIA_PCI)
  26                 dm_pci_read_config8(dev->parent,
  27                                     pirq_linkno_to_reg(link, base), &pirq);
  28         else
  29                 pirq = readb((uintptr_t)priv->ibase +
  30                              pirq_linkno_to_reg(link, base));
  31
  32         pirq &= 0xf;
  33
  34         /* IRQ# 0/1/2/8/13 are reserved */
  35         if (pirq < 3 || pirq == 8 || pirq == 13)
  36                 return false;
  37
  38         return pirq == irq ? true : false;
  39 }
  40
  41 int pirq_translate_link(struct udevice *dev, int link)
  42 {
  43         struct irq_router *priv = dev_get_priv(dev);
  44
  45         return pirq_reg_to_linkno(link, priv->link_base);
  46 }
  47
  48 void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
  49 {
  50         struct irq_router *priv = dev_get_priv(dev);
  51         int base = priv->link_base;
  52
  53         /* IRQ# 0/1/2/8/13 are reserved */
  54         if (irq < 3 || irq == 8 || irq == 13)
  55                 return;
  56
  57         if (priv->config == PIRQ_VIA_PCI)
  58                 dm_pci_write_config8(dev->parent,
  59                                      pirq_linkno_to_reg(link, base), irq);
  60         else
  61                 writeb(irq, (uintptr_t)priv->ibase +
  62                        pirq_linkno_to_reg(link, base));
  63 }
  64
  65 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  66                                         int entry_num, int bus, int device)
  67 {
  68         struct irq_info *slot = slot_base;
  69         int i;
  70
  71         for (i = 0; i < entry_num; i++) {
  72                 if (slot->bus == bus && slot->devfn == (device << 3))
  73                         break;
  74                 slot++;
  75         }
  76
  77         return (i == entry_num) ? NULL : slot;
  78 }
  79
  80 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
  81                                  int bus, int device, int pin, int pirq)
  82 {
  83         slot->bus = bus;
  84         slot->devfn = (device << 3) | 0;
  85         slot->irq[pin - 1].link = pirq_linkno_to_reg(pirq, priv->link_base);
  86         slot->irq[pin - 1].bitmap = priv->irq_mask;
  87 }
  88
  89 static int create_pirq_routing_table(struct udevice *dev)
  90 {
  91         struct irq_router *priv = dev_get_priv(dev);
  92         const void *blob = gd->fdt_blob;
  93         int node;
  94         int len, count;
  95         const u32 *cell;
  96         struct irq_routing_table *rt;
  97         struct irq_info *slot, *slot_base;
  98         int irq_entries = 0;
  99         int i;
 100         int ret;
 101
 102         node = dev_of_offset(dev);
 103
 104         /* extract the bdf from fdt_pci_addr */
 105         priv->bdf = dm_pci_get_bdf(dev->parent);
 106
 107         ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
 108         if (!ret) {
 109                 priv->config = PIRQ_VIA_PCI;
 110         } else {
 111                 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
 112                                             "ibase");
 113                 if (!ret)
 114                         priv->config = PIRQ_VIA_IBASE;
 115                 else
 116                         return -EINVAL;
 117         }
 118
 119         cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
 120         if (!cell || len != 8)
 121                 return -EINVAL;
 122         priv->link_base = fdt_addr_to_cpu(cell[0]);
 123         priv->link_num = fdt_addr_to_cpu(cell[1]);
 124         if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
 125                 debug("Limiting supported PIRQ link number from %d to %d\n",
 126                       priv->link_num, CONFIG_MAX_PIRQ_LINKS);
 127                 priv->link_num = CONFIG_MAX_PIRQ_LINKS;
 128         }
 129
 130         priv->irq_mask = fdtdec_get_int(blob, node,
 131                                         "intel,pirq-mask", PIRQ_BITMAP);
 132
 133         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
 134                 /* Reserve IRQ9 for SCI */
 135                 priv->irq_mask &= ~(1 << 9);
 136         }
 137
 138         if (priv->config == PIRQ_VIA_IBASE) {
 139                 int ibase_off;
 140
 141                 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
 142                 if (!ibase_off)
 143                         return -EINVAL;
 144
 145                 /*
 146                  * Here we assume that the IBASE register has already been
 147                  * properly configured by U-Boot before.
 148                  *
 149                  * By 'valid' we mean:
 150                  *   1) a valid memory space carved within system memory space
 151                  *      assigned to IBASE register block.
 152                  *   2) memory range decoding is enabled.
 153                  * Hence we don't do any santify test here.
 154                  */
 155                 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 156                 priv->ibase &= ~0xf;
 157         }
 158
 159         priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
 160         priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
 161
 162         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 163         if (!cell || len % sizeof(struct pirq_routing))
 164                 return -EINVAL;
 165         count = len / sizeof(struct pirq_routing);
 166
 167         rt = calloc(1, sizeof(struct irq_routing_table));
 168         if (!rt)
 169                 return -ENOMEM;
 170
 171         /* Populate the PIRQ table fields */
 172         rt->signature = PIRQ_SIGNATURE;
 173         rt->version = PIRQ_VERSION;
 174         rt->rtr_bus = PCI_BUS(priv->bdf);
 175         rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
 176         rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 177         rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 178
 179         slot_base = rt->slots;
 180
 181         /* Now fill in the irq_info entries in the PIRQ table */
 182         for (i = 0; i < count;
 183              i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
 184                 struct pirq_routing pr;
 185
 186                 pr.bdf = fdt_addr_to_cpu(cell[0]);
 187                 pr.pin = fdt_addr_to_cpu(cell[1]);
 188                 pr.pirq = fdt_addr_to_cpu(cell[2]);
 189
 190                 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
 191                       i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 192                       PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
 193                       'A' + pr.pirq);
 194
 195                 slot = check_dup_entry(slot_base, irq_entries,
 196                                        PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 197                 if (slot) {
 198                         debug("found entry for bus %d device %d, ",
 199                               PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 200
 201                         if (slot->irq[pr.pin - 1].link) {
 202                                 debug("skipping\n");
 203
 204                                 /*
 205                                  * Sanity test on the routed PIRQ pin
 206                                  *
 207                                  * If they don't match, show a warning to tell
 208                                  * there might be something wrong with the PIRQ
 209                                  * routing information in the device tree.
 210                                  */
 211                                 if (slot->irq[pr.pin - 1].link !=
 212                                     pirq_linkno_to_reg(pr.pirq, priv->link_base))
 213                                         debug("WARNING: Inconsistent PIRQ routing information\n");
 214                                 continue;
 215                         }
 216                 } else {
 217                         slot = slot_base + irq_entries++;
 218                 }
 219                 debug("writing INT%c\n", 'A' + pr.pin - 1);
 220                 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 221                               pr.pin, pr.pirq);
 222         }
 223
 224         rt->size = irq_entries * sizeof(struct irq_info) + 32;
 225
 226         /* Fix up the table checksum */
 227         rt->checksum = table_compute_checksum(rt, rt->size);
 228
 229         gd->arch.pirq_routing_table = rt;
 230
 231         return 0;
 232 }
 233
 234 static void irq_enable_sci(struct udevice *dev)
 235 {
 236         struct irq_router *priv = dev_get_priv(dev);
 237
 238         if (priv->actl_8bit) {
 239                 /* Bit7 must be turned on to enable ACPI */
 240                 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
 241         } else {
 242                 /* Write 0 to enable SCI on IRQ9 */
 243                 if (priv->config == PIRQ_VIA_PCI)
 244                         dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
 245                 else
 246                         writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
 247         }
 248 }
 249
 250 int irq_router_probe(struct udevice *dev)
 251 {
 252         int ret;
 253
 254         ret = create_pirq_routing_table(dev);
 255         if (ret) {
 256                 debug("Failed to create pirq routing table\n");
 257                 return ret;
 258         }
 259         /* Route PIRQ */
 260         pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
 261                         get_irq_slot_count(gd->arch.pirq_routing_table));
 262
 263         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
 264                 irq_enable_sci(dev);
 265
 266         return 0;
 267 }
 268
 269 ulong write_pirq_routing_table(ulong addr)
 270 {
 271         if (!gd->arch.pirq_routing_table)
 272                 return addr;
 273
 274         return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
 275 }
 276
 277 static const struct udevice_id irq_router_ids[] = {
 278         { .compatible = "intel,irq-router" },
 279         { }
 280 };
 281
 282 U_BOOT_DRIVER(irq_router_drv) = {
 283         .name           = "intel_irq",
 284         .id             = UCLASS_IRQ,
 285         .of_match       = irq_router_ids,
 286         .probe          = irq_router_probe,
 287         .priv_auto_alloc_size = sizeof(struct irq_router),
 288 };
 289
 290 UCLASS_DRIVER(irq) = {
 291         .id             = UCLASS_IRQ,
 292         .name           = "irq",
 293 };