git.sur5r.net Git - u-boot/blob - arch/x86/cpu/irq.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <asm/irq.h>
  14 #include <asm/pci.h>
  15 #include <asm/pirq_routing.h>
  16 #include <asm/tables.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct irq_routing_table *pirq_routing_table;
  21
  22 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
  23 {
  24         struct irq_router *priv = dev_get_priv(dev);
  25         u8 pirq;
  26         int base = priv->link_base;
  27
  28         if (priv->config == PIRQ_VIA_PCI)
  29                 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
  30         else
  31                 pirq = readb(priv->ibase + LINK_N2V(link, base));
  32
  33         pirq &= 0xf;
  34
  35         /* IRQ# 0/1/2/8/13 are reserved */
  36         if (pirq < 3 || pirq == 8 || pirq == 13)
  37                 return false;
  38
  39         return pirq == irq ? true : false;
  40 }
  41
  42 int pirq_translate_link(struct udevice *dev, int link)
  43 {
  44         struct irq_router *priv = dev_get_priv(dev);
  45
  46         return LINK_V2N(link, priv->link_base);
  47 }
  48
  49 void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
  50 {
  51         struct irq_router *priv = dev_get_priv(dev);
  52         int base = priv->link_base;
  53
  54         /* IRQ# 0/1/2/8/13 are reserved */
  55         if (irq < 3 || irq == 8 || irq == 13)
  56                 return;
  57
  58         if (priv->config == PIRQ_VIA_PCI)
  59                 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
  60         else
  61                 writeb(irq, priv->ibase + LINK_N2V(link, base));
  62 }
  63
  64 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  65                                         int entry_num, int bus, int device)
  66 {
  67         struct irq_info *slot = slot_base;
  68         int i;
  69
  70         for (i = 0; i < entry_num; i++) {
  71                 if (slot->bus == bus && slot->devfn == (device << 3))
  72                         break;
  73                 slot++;
  74         }
  75
  76         return (i == entry_num) ? NULL : slot;
  77 }
  78
  79 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
  80                                  int bus, int device, int pin, int pirq)
  81 {
  82         slot->bus = bus;
  83         slot->devfn = (device << 3) | 0;
  84         slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
  85         slot->irq[pin - 1].bitmap = priv->irq_mask;
  86 }
  87
  88 static int create_pirq_routing_table(struct udevice *dev)
  89 {
  90         struct irq_router *priv = dev_get_priv(dev);
  91         const void *blob = gd->fdt_blob;
  92         int node;
  93         int len, count;
  94         const u32 *cell;
  95         struct irq_routing_table *rt;
  96         struct irq_info *slot, *slot_base;
  97         int irq_entries = 0;
  98         int i;
  99         int ret;
 100
 101         node = dev->of_offset;
 102
 103         /* extract the bdf from fdt_pci_addr */
 104         priv->bdf = dm_pci_get_bdf(dev->parent);
 105
 106         ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
 107         if (!ret) {
 108                 priv->config = PIRQ_VIA_PCI;
 109         } else {
 110                 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
 111                                             "ibase");
 112                 if (!ret)
 113                         priv->config = PIRQ_VIA_IBASE;
 114                 else
 115                         return -EINVAL;
 116         }
 117
 118         ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
 119         if (ret == -1)
 120                 return ret;
 121         priv->link_base = ret;
 122
 123         priv->irq_mask = fdtdec_get_int(blob, node,
 124                                         "intel,pirq-mask", PIRQ_BITMAP);
 125
 126         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
 127                 /* Reserve IRQ9 for SCI */
 128                 priv->irq_mask &= ~(1 << 9);
 129         }
 130
 131         if (priv->config == PIRQ_VIA_IBASE) {
 132                 int ibase_off;
 133
 134                 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
 135                 if (!ibase_off)
 136                         return -EINVAL;
 137
 138                 /*
 139                  * Here we assume that the IBASE register has already been
 140                  * properly configured by U-Boot before.
 141                  *
 142                  * By 'valid' we mean:
 143                  *   1) a valid memory space carved within system memory space
 144                  *      assigned to IBASE register block.
 145                  *   2) memory range decoding is enabled.
 146                  * Hence we don't do any santify test here.
 147                  */
 148                 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 149                 priv->ibase &= ~0xf;
 150         }
 151
 152         priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
 153         priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
 154
 155         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 156         if (!cell || len % sizeof(struct pirq_routing))
 157                 return -EINVAL;
 158         count = len / sizeof(struct pirq_routing);
 159
 160         rt = calloc(1, sizeof(struct irq_routing_table));
 161         if (!rt)
 162                 return -ENOMEM;
 163
 164         /* Populate the PIRQ table fields */
 165         rt->signature = PIRQ_SIGNATURE;
 166         rt->version = PIRQ_VERSION;
 167         rt->rtr_bus = PCI_BUS(priv->bdf);
 168         rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
 169         rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 170         rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 171
 172         slot_base = rt->slots;
 173
 174         /* Now fill in the irq_info entries in the PIRQ table */
 175         for (i = 0; i < count;
 176              i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
 177                 struct pirq_routing pr;
 178
 179                 pr.bdf = fdt_addr_to_cpu(cell[0]);
 180                 pr.pin = fdt_addr_to_cpu(cell[1]);
 181                 pr.pirq = fdt_addr_to_cpu(cell[2]);
 182
 183                 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
 184                       i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 185                       PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
 186                       'A' + pr.pirq);
 187
 188                 slot = check_dup_entry(slot_base, irq_entries,
 189                                        PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 190                 if (slot) {
 191                         debug("found entry for bus %d device %d, ",
 192                               PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 193
 194                         if (slot->irq[pr.pin - 1].link) {
 195                                 debug("skipping\n");
 196
 197                                 /*
 198                                  * Sanity test on the routed PIRQ pin
 199                                  *
 200                                  * If they don't match, show a warning to tell
 201                                  * there might be something wrong with the PIRQ
 202                                  * routing information in the device tree.
 203                                  */
 204                                 if (slot->irq[pr.pin - 1].link !=
 205                                         LINK_N2V(pr.pirq, priv->link_base))
 206                                         debug("WARNING: Inconsistent PIRQ routing information\n");
 207                                 continue;
 208                         }
 209                 } else {
 210                         slot = slot_base + irq_entries++;
 211                 }
 212                 debug("writing INT%c\n", 'A' + pr.pin - 1);
 213                 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 214                               pr.pin, pr.pirq);
 215         }
 216
 217         rt->size = irq_entries * sizeof(struct irq_info) + 32;
 218
 219         /* Fix up the table checksum */
 220         rt->checksum = table_compute_checksum(rt, rt->size);
 221
 222         pirq_routing_table = rt;
 223
 224         return 0;
 225 }
 226
 227 static void irq_enable_sci(struct udevice *dev)
 228 {
 229         struct irq_router *priv = dev_get_priv(dev);
 230
 231         if (priv->actl_8bit) {
 232                 /* Bit7 must be turned on to enable ACPI */
 233                 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
 234         } else {
 235                 /* Write 0 to enable SCI on IRQ9 */
 236                 if (priv->config == PIRQ_VIA_PCI)
 237                         dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
 238                 else
 239                         writel(0, priv->ibase + priv->actl_addr);
 240         }
 241 }
 242
 243 int irq_router_common_init(struct udevice *dev)
 244 {
 245         int ret;
 246
 247         ret = create_pirq_routing_table(dev);
 248         if (ret) {
 249                 debug("Failed to create pirq routing table\n");
 250                 return ret;
 251         }
 252         /* Route PIRQ */
 253         pirq_route_irqs(dev, pirq_routing_table->slots,
 254                         get_irq_slot_count(pirq_routing_table));
 255
 256         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
 257                 irq_enable_sci(dev);
 258
 259         return 0;
 260 }
 261
 262 int irq_router_probe(struct udevice *dev)
 263 {
 264         return irq_router_common_init(dev);
 265 }
 266
 267 u32 write_pirq_routing_table(u32 addr)
 268 {
 269         if (!pirq_routing_table)
 270                 return addr;
 271
 272         return copy_pirq_routing_table(addr, pirq_routing_table);
 273 }
 274
 275 static const struct udevice_id irq_router_ids[] = {
 276         { .compatible = "intel,irq-router" },
 277         { }
 278 };
 279
 280 U_BOOT_DRIVER(irq_router_drv) = {
 281         .name           = "intel_irq",
 282         .id             = UCLASS_IRQ,
 283         .of_match       = irq_router_ids,
 284         .probe          = irq_router_probe,
 285         .priv_auto_alloc_size = sizeof(struct irq_router),
 286 };
 287
 288 UCLASS_DRIVER(irq) = {
 289         .id             = UCLASS_IRQ,
 290         .name           = "irq",
 291 };