2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/lapic.h>
14 #include <asm/arch/bd82x6x.h>
15 #include <asm/arch/model_206ax.h>
16 #include <asm/arch/pch.h>
17 #include <asm/arch/sandybridge.h>
19 #define BIOS_CTRL 0xdc
21 void bd82x6x_pci_init(pci_dev_t dev)
26 debug("bd82x6x PCI init.\n");
27 /* Enable Bus Master */
28 reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
29 reg16 |= PCI_COMMAND_MASTER;
30 x86_pci_write_config16(dev, PCI_COMMAND, reg16);
32 /* This device has no interrupt */
33 x86_pci_write_config8(dev, INTR, 0xff);
35 /* disable parity error response and SERR */
36 reg16 = x86_pci_read_config16(dev, BCTRL);
39 x86_pci_write_config16(dev, BCTRL, reg16);
41 /* Master Latency Count must be set to 0x04! */
42 reg8 = x86_pci_read_config8(dev, SMLT);
45 x86_pci_write_config8(dev, SMLT, reg8);
47 /* Will this improve throughput of bus masters? */
48 x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
50 /* Clear errors in status registers */
51 reg16 = x86_pci_read_config16(dev, PSTS);
52 /* reg16 |= 0xf900; */
53 x86_pci_write_config16(dev, PSTS, reg16);
55 reg16 = x86_pci_read_config16(dev, SECSTS);
56 /* reg16 |= 0xf900; */
57 x86_pci_write_config16(dev, SECSTS, reg16);
60 static int bd82x6x_probe(struct udevice *dev)
62 const void *blob = gd->fdt_blob;
63 struct pci_controller *hose;
64 struct x86_cpu_priv *cpu;
65 int sata_node, gma_node;
68 hose = pci_bus_to_hose(0);
69 lpc_enable(PCH_LPC_DEV);
70 lpc_init(hose, PCH_LPC_DEV);
71 sata_node = fdtdec_next_compatible(blob, 0,
72 COMPAT_INTEL_PANTHERPOINT_AHCI);
74 debug("%s: Cannot find SATA node\n", __func__);
77 bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
78 bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
79 bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
81 cpu = calloc(1, sizeof(*cpu));
84 model_206ax_init(cpu);
86 gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
88 debug("%s: Cannot find GMA node\n", __func__);
91 ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
94 ret = gma_func0_init(dev, blob, gma_node);
101 /* TODO(sjg@chromium.org): Move this to the PCH init() method */
102 int bd82x6x_init(void)
104 const void *blob = gd->fdt_blob;
107 sata_node = fdtdec_next_compatible(blob, 0,
108 COMPAT_INTEL_PANTHERPOINT_AHCI);
110 debug("%s: Cannot find SATA node\n", __func__);
114 bd82x6x_pci_init(PCH_DEV);
115 bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
116 northbridge_enable(PCH_DEV);
117 northbridge_init(PCH_DEV);
122 static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
126 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
127 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
128 rcba = rcba & 0xffffc000;
129 *sbasep = rcba + 0x3800;
134 static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
139 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
143 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
144 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
146 bios_cntl &= ~BIOS_CTRL_BIOSWE;
149 bios_cntl |= BIOS_CTRL_BIOSWE;
150 bios_cntl &= ~BIT(5);
152 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
157 static const struct pch_ops bd82x6x_pch_ops = {
158 .get_sbase = bd82x6x_pch_get_sbase,
159 .get_version = bd82x6x_pch_get_version,
160 .set_spi_protect = bd82x6x_set_spi_protect,
163 static const struct udevice_id bd82x6x_ids[] = {
164 { .compatible = "intel,bd82x6x" },
168 U_BOOT_DRIVER(bd82x6x_drv) = {
171 .of_match = bd82x6x_ids,
172 .probe = bd82x6x_probe,
173 .ops = &bd82x6x_pch_ops,