2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/intel_regs.h>
15 #include <asm/lapic.h>
16 #include <asm/lpc_common.h>
18 #include <asm/arch/model_206ax.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/sandybridge.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define GPIO_BASE 0x48
25 #define BIOS_CTRL 0xdc
27 #ifndef CONFIG_HAVE_FSP
28 static int pch_revision_id = -1;
29 static int pch_type = -1;
32 * pch_silicon_revision() - Read silicon revision ID from the PCH
35 * @return silicon revision ID
37 static int pch_silicon_revision(struct udevice *dev)
41 if (pch_revision_id < 0) {
42 dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
43 pch_revision_id = val;
46 return pch_revision_id;
49 int pch_silicon_type(struct udevice *dev)
54 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
62 * pch_silicon_supported() - Check if a certain revision is supported
66 * @rev: Minimum required resion
67 * @return 0 if not supported, 1 if supported
69 static int pch_silicon_supported(struct udevice *dev, int type, int rev)
71 int cur_type = pch_silicon_type(dev);
72 int cur_rev = pch_silicon_revision(dev);
76 /* CougarPoint minimum revision */
77 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
79 /* PantherPoint any revision */
80 if (cur_type == PCH_TYPE_PPT)
85 /* PantherPoint minimum revision */
86 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
94 #define IOBP_RETRY 1000
95 static inline int iobp_poll(void)
97 unsigned try = IOBP_RETRY;
101 data = readl(RCB_REG(IOBPS));
107 printf("IOBP timeout\n");
111 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
116 /* Set the address */
117 writel(address, RCB_REG(IOBPIRI));
120 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
121 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
123 writel(IOBPS_READ_AX, RCB_REG(IOBPS));
128 data = readl(RCB_REG(IOBPD));
132 /* Check for successful transaction */
133 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
134 printf("IOBP read 0x%08x failed\n", address);
138 /* Update the data */
143 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
144 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
146 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
150 /* Write IOBP data */
151 writel(data, RCB_REG(IOBPD));
156 static int bd82x6x_probe(struct udevice *dev)
158 if (!(gd->flags & GD_FLG_RELOC))
161 /* Cause the SATA device to do its init */
162 uclass_first_device(UCLASS_AHCI, &dev);
166 #endif /* CONFIG_HAVE_FSP */
168 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
172 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
173 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
174 rcba = rcba & 0xffffc000;
175 *sbasep = rcba + 0x3800;
180 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
182 return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
185 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
190 * GPIO_BASE moved to its current offset with ICH6, but prior to
191 * that it was unused (or undocumented). Check that it looks
192 * okay: not all ones or zeros.
194 * Note we don't need check bit0 here, because the Tunnel Creek
195 * GPIO base address register bit0 is reserved (read returns 0),
196 * while on the Ivybridge the bit0 is used to indicate it is an
199 dm_pci_read_config32(dev, GPIO_BASE, &base);
200 if (base == 0x00000000 || base == 0xffffffff) {
201 debug("%s: unexpected BASE value\n", __func__);
206 * Okay, I guess we're looking at the right device. The actual
207 * GPIO registers are in the PCI device's I/O space, starting
208 * at the offset that we just read. Bit 0 indicates that it's
209 * an I/O address, not a memory address, so mask that off.
211 *gbasep = base & 1 ? base & ~3 : base & ~15;
216 static const struct pch_ops bd82x6x_pch_ops = {
217 .get_spi_base = bd82x6x_pch_get_spi_base,
218 .set_spi_protect = bd82x6x_set_spi_protect,
219 .get_gpio_base = bd82x6x_get_gpio_base,
222 static const struct udevice_id bd82x6x_ids[] = {
223 { .compatible = "intel,bd82x6x" },
227 U_BOOT_DRIVER(bd82x6x_drv) = {
230 .of_match = bd82x6x_ids,
231 #ifndef CONFIG_HAVE_FSP
232 .probe = bd82x6x_probe,
234 .ops = &bd82x6x_pch_ops,