2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
6 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
7 * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
8 * Copyright (C) 2007-2008 coresystems GmbH
9 * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/msr-index.h>
18 #include <asm/processor-flags.h>
19 #include <asm/arch/microcode.h>
21 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
24 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
25 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
27 /* Cache 4GB - MRC_SIZE_KB for MRC */
28 #define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
29 #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
30 #define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
32 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
34 #define NOEVICTMOD_MSR 0x2e0
37 * Note: ebp must not be touched in this code as it holds the BIST
38 * value (built-in self test). We preserve this value until it can
39 * be written to global_data when CAR is ready for use.
43 post_code(POST_CAR_START)
45 /* Send INIT IPI to all excluding ourself */
46 movl $0x000C4500, %eax
47 movl $0xFEE00300, %esi
50 /* TODO: Load microcode later - the 'no eviction' mode breaks this */
51 movl $MSR_IA32_UCODE_WRITE, %ecx
53 movl $_dt_ucode_base_size, %eax
55 addl $UCODE_HEADER_LEN, %eax
58 post_code(POST_CAR_SIPI)
59 /* Zero out all fixed range and variable range MTRRs */
60 movl $mtrr_table, %esi
61 movl $((mtrr_table_end - mtrr_table) / 2), %edi
72 post_code(POST_CAR_MTRR)
73 /* Configure the default memory type to uncacheable */
74 movl $MTRR_DEF_TYPE_MSR, %ecx
76 andl $(~0x00000cff), %eax
79 post_code(POST_CAR_UNCACHEABLE)
80 /* Set Cache-as-RAM base address */
81 movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
82 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
86 post_code(POST_CAR_BASE_ADDRESS)
87 /* Set Cache-as-RAM mask */
88 movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
89 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
90 movl $CPU_PHYSMASK_HI, %edx
93 post_code(POST_CAR_MASK)
96 movl $MTRR_DEF_TYPE_MSR, %ecx
98 orl $MTRR_DEF_TYPE_EN, %eax
101 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
103 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
107 /* enable the 'no eviction' mode */
108 movl $NOEVICTMOD_MSR, %ecx
114 /* Clear the cache memory region. This will also fill up the cache */
115 movl $CACHE_AS_RAM_BASE, %esi
117 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
121 /* enable the 'no eviction run' state */
122 movl $NOEVICTMOD_MSR, %ecx
127 post_code(POST_CAR_FILL)
128 /* Enable Cache-as-RAM mode by disabling cache */
130 orl $X86_CR0_CD, %eax
133 /* Enable cache for our code in Flash because we do XIP here */
134 movl $MTRR_PHYS_BASE_MSR(1), %ecx
136 movl $car_init_ret, %eax
137 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
138 orl $MTRR_TYPE_WRPROT, %eax
141 movl $MTRR_PHYS_MASK_MSR(1), %ecx
142 movl $CPU_PHYSMASK_HI, %edx
143 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
146 post_code(POST_CAR_ROM_CACHE)
147 #ifdef CONFIG_CACHE_MRC_BIN
148 /* Enable caching for ram init code to run faster */
149 movl $MTRR_PHYS_BASE_MSR(2), %ecx
150 movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
153 movl $MTRR_PHYS_MASK_MSR(2), %ecx
154 movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
155 movl $CPU_PHYSMASK_HI, %edx
159 post_code(POST_CAR_MRC_CACHE)
162 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
165 post_code(POST_CAR_CPU_CACHE)
167 /* All CPUs need to be in Wait for SIPI state */
180 orl $X86_CR0_CD, %eax
184 movl $MTRR_DEF_TYPE_MSR, %ecx
186 andl $(~MTRR_DEF_TYPE_EN), %eax
189 /* Disable the no-eviction run state */
190 movl NOEVICTMOD_MSR, %ecx
197 /* Disable the no-eviction mode */
202 #ifdef CONFIG_CACHE_MRC_BIN
203 /* Clear the MTRR that was used to cache MRC */
206 movl $MTRR_PHYS_BASE_MSR(2), %ecx
208 movl $MTRR_PHYS_MASK_MSR(2), %ecx
213 movl $MTRR_DEF_TYPE_MSR, %ecx
215 orl $MTRR_DEF_TYPE_EN, %eax
224 .word 0x250, 0x258, 0x259
225 .word 0x268, 0x269, 0x26A
226 .word 0x26B, 0x26C, 0x26D
229 .word 0x200, 0x201, 0x202, 0x203
230 .word 0x204, 0x205, 0x206, 0x207
231 .word 0x208, 0x209, 0x20A, 0x20B
232 .word 0x20C, 0x20D, 0x20E, 0x20F
233 .word 0x210, 0x211, 0x212, 0x213
238 /* These next two fields are filled in by ifdtool */
239 .long 0 /* microcode base */
240 .long 0 /* microcode size */