2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
6 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
7 * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
8 * Copyright (C) 2007-2008 coresystems GmbH
9 * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0
17 #include <asm/processor-flags.h>
19 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
20 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
22 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
23 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
25 /* Cache 4GB - MRC_SIZE_KB for MRC */
26 #define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
27 #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
28 #define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
30 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
32 #define NOEVICTMOD_MSR 0x2e0
35 * Note: ebp must not be touched in this code as it holds the BIST
36 * value (built-in self test). We preserve this value until it can
37 * be written to global_data when CAR is ready for use.
41 post_code(POST_CAR_START)
43 /* Send INIT IPI to all excluding ourself */
44 movl $0x000C4500, %eax
45 movl $0xFEE00300, %esi
48 post_code(POST_CAR_SIPI)
49 /* Zero out all fixed range and variable range MTRRs */
50 movl $mtrr_table, %esi
51 movl $((mtrr_table_end - mtrr_table) / 2), %edi
62 post_code(POST_CAR_MTRR)
63 /* Configure the default memory type to uncacheable */
64 movl $MTRR_DEF_TYPE_MSR, %ecx
66 andl $(~0x00000cff), %eax
69 post_code(POST_CAR_UNCACHEABLE)
70 /* Set Cache-as-RAM base address */
71 movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
72 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
76 post_code(POST_CAR_BASE_ADDRESS)
77 /* Set Cache-as-RAM mask */
78 movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
79 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
80 movl $CPU_PHYSMASK_HI, %edx
83 post_code(POST_CAR_MASK)
86 movl $MTRR_DEF_TYPE_MSR, %ecx
88 orl $MTRR_DEF_TYPE_EN, %eax
91 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
93 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
97 /* enable the 'no eviction' mode */
98 movl $NOEVICTMOD_MSR, %ecx
104 /* Clear the cache memory region. This will also fill up the cache */
105 movl $CACHE_AS_RAM_BASE, %esi
107 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
111 /* enable the 'no eviction run' state */
112 movl $NOEVICTMOD_MSR, %ecx
117 post_code(POST_CAR_FILL)
118 /* Enable Cache-as-RAM mode by disabling cache */
120 orl $X86_CR0_CD, %eax
123 /* Enable cache for our code in Flash because we do XIP here */
124 movl $MTRR_PHYS_BASE_MSR(1), %ecx
126 movl $car_init_ret, %eax
127 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
128 orl $MTRR_TYPE_WRPROT, %eax
131 movl $MTRR_PHYS_MASK_MSR(1), %ecx
132 movl $CPU_PHYSMASK_HI, %edx
133 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
136 post_code(POST_CAR_ROM_CACHE)
137 #ifdef CONFIG_CACHE_MRC_BIN
138 /* Enable caching for ram init code to run faster */
139 movl $MTRR_PHYS_BASE_MSR(2), %ecx
140 movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
143 movl $MTRR_PHYS_MASK_MSR(2), %ecx
144 movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
145 movl $CPU_PHYSMASK_HI, %edx
149 post_code(POST_CAR_MRC_CACHE)
152 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
155 post_code(POST_CAR_CPU_CACHE)
157 /* All CPUs need to be in Wait for SIPI state */
168 .word 0x250, 0x258, 0x259
169 .word 0x268, 0x269, 0x26A
170 .word 0x26B, 0x26C, 0x26D
173 .word 0x200, 0x201, 0x202, 0x203
174 .word 0x204, 0x205, 0x206, 0x207
175 .word 0x208, 0x209, 0x20A, 0x20B
176 .word 0x20C, 0x20D, 0x20E, 0x20F
177 .word 0x210, 0x211, 0x212, 0x213