2 * Copyright (c) 2014 Google, Inc
4 * Graeme Russ, graeme.russ@gmail.com.
6 * Some portions from coreboot src/mainboard/google/link/romstage.c
7 * and src/cpu/intel/model_206ax/bootblock.c
8 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
11 * SPDX-License-Identifier: GPL-2.0
20 #include <asm/lapic.h>
25 #include <asm/processor.h>
26 #include <asm/arch/model_206ax.h>
27 #include <asm/arch/microcode.h>
28 #include <asm/arch/pch.h>
29 #include <asm/arch/sandybridge.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
35 /* Enable port 80 POST on LPC */
36 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
37 clrbits_le32(RCB_REG(GCS), 4);
41 * Enable Prefetching and Caching.
43 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
47 pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
49 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
50 pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
53 static int set_flex_ratio_to_tdp_nominal(void)
55 msr_t flex_ratio, msr;
58 /* Minimum CPU revision for configurable TDP support */
59 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
62 /* Check for Flex Ratio support */
63 flex_ratio = msr_read(MSR_FLEX_RATIO);
64 if (!(flex_ratio.lo & FLEX_RATIO_EN))
67 /* Check for >0 configurable TDPs */
68 msr = msr_read(MSR_PLATFORM_INFO);
69 if (((msr.hi >> 1) & 3) == 0)
72 /* Use nominal TDP ratio for flex ratio */
73 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
74 nominal_ratio = msr.lo & 0xff;
76 /* See if flex ratio is already set to nominal TDP ratio */
77 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
80 /* Set flex ratio to nominal TDP ratio */
81 flex_ratio.lo &= ~0xff00;
82 flex_ratio.lo |= nominal_ratio << 8;
83 flex_ratio.lo |= FLEX_RATIO_LOCK;
84 msr_write(MSR_FLEX_RATIO, flex_ratio);
86 /* Set flex ratio in soft reset data register bits 11:6 */
87 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
88 (nominal_ratio & 0x3f) << 6);
90 /* Set soft reset control to use register value */
91 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
93 /* Issue warm reset, will be "CPU only" due to soft reset data */
94 outb(0x0, PORT_RESET);
95 outb(SYS_RST | RST_CPU, PORT_RESET);
102 static void set_spi_speed(void)
106 /* Observe SPI Descriptor Component Section 0 */
107 writel(0x1000, RCB_REG(SPI_DESC_COMP0));
109 /* Extract the1 Write/Erase SPI Frequency from descriptor */
110 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
114 /* Set Software Sequence frequency to match */
115 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
118 int arch_cpu_init(void)
120 post_code(POST_CPU_INIT);
121 timer_set_base(rdtsc());
123 return x86_cpu_init_f();
126 int arch_cpu_init_dm(void)
128 const void *blob = gd->fdt_blob;
129 struct pci_controller *hose;
135 ret = uclass_get_device(UCLASS_PCI, 0, &bus);
140 hose = dev_get_uclass_priv(bus);
142 /* TODO(sjg@chromium.org): Get rid of gd->hose */
145 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
148 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
152 enable_spi_prefetch(hose, PCH_LPC_DEV);
154 /* This is already done in start.S, but let's do it in C */
155 enable_port80_on_lpc(hose, PCH_LPC_DEV);
160 * We should do as little as possible before the serial console is
161 * up. Perhaps this should move to later. Our next lot of init
162 * happens in print_cpuinfo() when we have a console
164 ret = set_flex_ratio_to_tdp_nominal();
171 static int enable_smbus(void)
176 /* Set the SMBus device statically. */
177 dev = PCI_BDF(0x0, 0x1f, 0x3);
179 /* Check to make sure we've got the right device. */
180 value = x86_pci_read_config16(dev, 0x0);
181 if (value != 0x8086) {
182 printf("SMBus controller not found\n");
186 /* Set SMBus I/O base. */
187 x86_pci_write_config32(dev, SMB_BASE,
188 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
190 /* Set SMBus enable. */
191 x86_pci_write_config8(dev, HOSTC, HST_EN);
193 /* Set SMBus I/O space enable. */
194 x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
196 /* Disable interrupt generation. */
197 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
199 /* Clear any lingering errors, so transactions can run. */
200 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
201 debug("SMBus controller enabled\n");
206 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
207 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
208 #define PCH_XHCI_TEMP_BAR0 0xe8001000
211 * Setup USB controller MMIO BAR to prevent the reference code from
212 * resetting the controller.
214 * The BAR will be re-assigned during device enumeration so these are only
217 * This is used to speed up the resume path.
219 static void enable_usb_bar(void)
221 pci_dev_t usb0 = PCH_EHCI1_DEV;
222 pci_dev_t usb1 = PCH_EHCI2_DEV;
223 pci_dev_t usb3 = PCH_XHCI_DEV;
226 /* USB Controller 1 */
227 x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
228 PCH_EHCI0_TEMP_BAR0);
229 cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
230 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
231 x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
233 /* USB Controller 1 */
234 x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
235 PCH_EHCI1_TEMP_BAR0);
236 cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
237 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
238 x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
240 /* USB3 Controller */
241 x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
243 cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
244 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
245 x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
248 static int report_bist_failure(void)
250 if (gd->arch.bist != 0) {
251 post_code(POST_BIST_FAILURE);
252 printf("BIST failed: %08x\n", gd->arch.bist);
259 int print_cpuinfo(void)
261 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
262 char processor_name[CPU_MAX_NAME_LEN];
268 /* Halt if there was a built in self test failure */
269 ret = report_bist_failure();
275 ret = microcode_update_intel();
279 /* Enable upper 128bytes of CMOS */
280 writel(1 << 2, RCB_REG(RC));
282 /* TODO: cmos_post_init() */
283 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
284 debug("soft reset detected\n");
285 boot_mode = PEI_BOOT_SOFT_RESET;
287 /* System is not happy after keyboard reset... */
288 debug("Issuing CF9 warm reset\n");
292 /* Early chipset init required before RAM init can work */
293 sandybridge_early_init(SANDYBRIDGE_MOBILE);
295 /* Check PM1_STS[15] to see if we are waking from Sx */
296 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
298 /* Read PM1_CNT[12:10] to determine which Sx state */
299 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
301 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
302 #if CONFIG_HAVE_ACPI_RESUME
303 debug("Resume from S3 detected.\n");
304 boot_mode = PEI_BOOT_RESUME;
305 /* Clear SLP_TYPE. This will break stage2 but
306 * we care for that when we get there.
308 outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
310 debug("Resume from S3 detected, but disabled.\n");
314 * TODO: An indication of life might be possible here (e.g.
318 post_code(POST_EARLY_INIT);
320 /* Enable SPD ROMs and DDR-III DRAM */
321 ret = enable_smbus();
325 /* Prepare USB controller early in S3 resume */
326 if (boot_mode == PEI_BOOT_RESUME)
329 gd->arch.pei_boot_mode = boot_mode;
331 /* TODO: Move this to the board or driver */
332 x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
333 x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
335 /* Print processor name */
336 name = cpu_get_name(processor_name);
337 printf("CPU: %s\n", name);
339 post_code(POST_CPU_INFO);
344 void board_debug_uart_init(void)
346 /* This enables the debug UART */
347 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,