2 * Copyright (c) 2014 Google, Inc
4 * Graeme Russ, graeme.russ@gmail.com.
6 * Some portions from coreboot src/mainboard/google/link/romstage.c
7 * and src/cpu/intel/model_206ax/bootblock.c
8 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
11 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/lapic.h>
24 #include <asm/processor.h>
25 #include <asm/arch/model_206ax.h>
26 #include <asm/arch/microcode.h>
27 #include <asm/arch/pch.h>
28 #include <asm/arch/sandybridge.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
34 /* Enable port 80 POST on LPC */
35 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
36 clrbits_le32(RCB_REG(GCS), 4);
40 * Enable Prefetching and Caching.
42 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
46 pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
48 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
49 pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
52 static void set_var_mtrr(
53 unsigned reg, unsigned base, unsigned size, unsigned type)
56 /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
57 /* FIXME: It only support 4G less range */
58 wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
59 wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
60 (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
63 static void enable_rom_caching(void)
66 set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
69 /* Enable Variable MTRRs */
70 wrmsr(MTRRdefType_MSR, 0x800, 0);
73 static int set_flex_ratio_to_tdp_nominal(void)
75 msr_t flex_ratio, msr;
78 /* Minimum CPU revision for configurable TDP support */
79 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
82 /* Check for Flex Ratio support */
83 flex_ratio = msr_read(MSR_FLEX_RATIO);
84 if (!(flex_ratio.lo & FLEX_RATIO_EN))
87 /* Check for >0 configurable TDPs */
88 msr = msr_read(MSR_PLATFORM_INFO);
89 if (((msr.hi >> 1) & 3) == 0)
92 /* Use nominal TDP ratio for flex ratio */
93 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
94 nominal_ratio = msr.lo & 0xff;
96 /* See if flex ratio is already set to nominal TDP ratio */
97 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
100 /* Set flex ratio to nominal TDP ratio */
101 flex_ratio.lo &= ~0xff00;
102 flex_ratio.lo |= nominal_ratio << 8;
103 flex_ratio.lo |= FLEX_RATIO_LOCK;
104 msr_write(MSR_FLEX_RATIO, flex_ratio);
106 /* Set flex ratio in soft reset data register bits 11:6 */
107 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
108 (nominal_ratio & 0x3f) << 6);
110 /* Set soft reset control to use register value */
111 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
113 /* Issue warm reset, will be "CPU only" due to soft reset data */
114 outb(0x0, PORT_RESET);
115 outb(0x6, PORT_RESET);
122 static void set_spi_speed(void)
126 /* Observe SPI Descriptor Component Section 0 */
127 writel(0x1000, RCB_REG(SPI_DESC_COMP0));
129 /* Extract the1 Write/Erase SPI Frequency from descriptor */
130 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
134 /* Set Software Sequence frequency to match */
135 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
138 int arch_cpu_init(void)
140 const void *blob = gd->fdt_blob;
141 struct pci_controller *hose;
145 post_code(POST_CPU_INIT);
146 timer_set_base(rdtsc());
148 ret = x86_cpu_init_f();
152 ret = pci_early_init_hose(&hose);
156 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
159 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
163 enable_spi_prefetch(hose, PCH_LPC_DEV);
165 /* This is already done in start.S, but let's do it in C */
166 enable_port80_on_lpc(hose, PCH_LPC_DEV);
168 /* already done in car.S */
170 enable_rom_caching();
175 * We should do as little as possible before the serial console is
176 * up. Perhaps this should move to later. Our next lot of init
177 * happens in print_cpuinfo() when we have a console
179 ret = set_flex_ratio_to_tdp_nominal();
186 static int enable_smbus(void)
191 /* Set the SMBus device statically. */
192 dev = PCI_BDF(0x0, 0x1f, 0x3);
194 /* Check to make sure we've got the right device. */
195 value = pci_read_config16(dev, 0x0);
196 if (value != 0x8086) {
197 printf("SMBus controller not found\n");
201 /* Set SMBus I/O base. */
202 pci_write_config32(dev, SMB_BASE,
203 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
205 /* Set SMBus enable. */
206 pci_write_config8(dev, HOSTC, HST_EN);
208 /* Set SMBus I/O space enable. */
209 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
211 /* Disable interrupt generation. */
212 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
214 /* Clear any lingering errors, so transactions can run. */
215 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
216 debug("SMBus controller enabled\n");
221 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
222 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
223 #define PCH_XHCI_TEMP_BAR0 0xe8001000
226 * Setup USB controller MMIO BAR to prevent the reference code from
227 * resetting the controller.
229 * The BAR will be re-assigned during device enumeration so these are only
232 * This is used to speed up the resume path.
234 static void enable_usb_bar(void)
236 pci_dev_t usb0 = PCH_EHCI1_DEV;
237 pci_dev_t usb1 = PCH_EHCI2_DEV;
238 pci_dev_t usb3 = PCH_XHCI_DEV;
241 /* USB Controller 1 */
242 pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
243 PCH_EHCI0_TEMP_BAR0);
244 cmd = pci_read_config32(usb0, PCI_COMMAND);
245 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
246 pci_write_config32(usb0, PCI_COMMAND, cmd);
248 /* USB Controller 1 */
249 pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
250 PCH_EHCI1_TEMP_BAR0);
251 cmd = pci_read_config32(usb1, PCI_COMMAND);
252 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
253 pci_write_config32(usb1, PCI_COMMAND, cmd);
255 /* USB3 Controller */
256 pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
258 cmd = pci_read_config32(usb3, PCI_COMMAND);
259 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
260 pci_write_config32(usb3, PCI_COMMAND, cmd);
263 static int report_bist_failure(void)
265 if (gd->arch.bist != 0) {
266 printf("BIST failed: %08x\n", gd->arch.bist);
273 int print_cpuinfo(void)
275 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
276 char processor_name[CPU_MAX_NAME_LEN];
282 /* Halt if there was a built in self test failure */
283 ret = report_bist_failure();
289 ret = microcode_update_intel();
290 if (ret && ret != -ENOENT && ret != -EEXIST)
293 /* Enable upper 128bytes of CMOS */
294 writel(1 << 2, RCB_REG(RC));
296 /* TODO: cmos_post_init() */
297 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
298 debug("soft reset detected\n");
299 boot_mode = PEI_BOOT_SOFT_RESET;
301 /* System is not happy after keyboard reset... */
302 debug("Issuing CF9 warm reset\n");
307 /* Early chipset init required before RAM init can work */
308 sandybridge_early_init(SANDYBRIDGE_MOBILE);
310 /* Check PM1_STS[15] to see if we are waking from Sx */
311 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
313 /* Read PM1_CNT[12:10] to determine which Sx state */
314 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
316 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
317 #if CONFIG_HAVE_ACPI_RESUME
318 debug("Resume from S3 detected.\n");
319 boot_mode = PEI_BOOT_RESUME;
320 /* Clear SLP_TYPE. This will break stage2 but
321 * we care for that when we get there.
323 outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
325 debug("Resume from S3 detected, but disabled.\n");
329 * TODO: An indication of life might be possible here (e.g.
333 post_code(POST_EARLY_INIT);
335 /* Enable SPD ROMs and DDR-III DRAM */
336 ret = enable_smbus();
340 /* Prepare USB controller early in S3 resume */
341 if (boot_mode == PEI_BOOT_RESUME)
344 gd->arch.pei_boot_mode = boot_mode;
346 /* TODO: Move this to the board or driver */
347 pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
348 pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
350 /* Print processor name */
351 name = cpu_get_name(processor_name);
352 printf("CPU: %s\n", name);
354 post_code(POST_CPU_INFO);