2 * Copyright (c) 2014 Google, Inc
4 * Graeme Russ, graeme.russ@gmail.com.
6 * Some portions from coreboot src/mainboard/google/link/romstage.c
7 * and src/cpu/intel/model_206ax/bootblock.c
8 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
11 * SPDX-License-Identifier: GPL-2.0
21 #include <asm/lapic.h>
26 #include <asm/processor.h>
27 #include <asm/arch/model_206ax.h>
28 #include <asm/arch/microcode.h>
29 #include <asm/arch/pch.h>
30 #include <asm/arch/sandybridge.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 static int set_flex_ratio_to_tdp_nominal(void)
36 msr_t flex_ratio, msr;
39 /* Minimum CPU revision for configurable TDP support */
40 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
43 /* Check for Flex Ratio support */
44 flex_ratio = msr_read(MSR_FLEX_RATIO);
45 if (!(flex_ratio.lo & FLEX_RATIO_EN))
48 /* Check for >0 configurable TDPs */
49 msr = msr_read(MSR_PLATFORM_INFO);
50 if (((msr.hi >> 1) & 3) == 0)
53 /* Use nominal TDP ratio for flex ratio */
54 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
55 nominal_ratio = msr.lo & 0xff;
57 /* See if flex ratio is already set to nominal TDP ratio */
58 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
61 /* Set flex ratio to nominal TDP ratio */
62 flex_ratio.lo &= ~0xff00;
63 flex_ratio.lo |= nominal_ratio << 8;
64 flex_ratio.lo |= FLEX_RATIO_LOCK;
65 msr_write(MSR_FLEX_RATIO, flex_ratio);
67 /* Set flex ratio in soft reset data register bits 11:6 */
68 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
69 (nominal_ratio & 0x3f) << 6);
71 /* Set soft reset control to use register value */
72 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
74 /* Issue warm reset, will be "CPU only" due to soft reset data */
75 outb(0x0, PORT_RESET);
76 outb(SYS_RST | RST_CPU, PORT_RESET);
83 int arch_cpu_init(void)
85 post_code(POST_CPU_INIT);
87 return x86_cpu_init_f();
90 int arch_cpu_init_dm(void)
92 struct pci_controller *hose;
93 struct udevice *bus, *dev;
97 ret = uclass_get_device(UCLASS_PCI, 0, &bus);
102 hose = dev_get_uclass_priv(bus);
104 /* TODO(sjg@chromium.org): Get rid of gd->hose */
107 ret = uclass_first_device(UCLASS_LPC, &dev);
112 * We should do as little as possible before the serial console is
113 * up. Perhaps this should move to later. Our next lot of init
114 * happens in print_cpuinfo() when we have a console
116 ret = set_flex_ratio_to_tdp_nominal();
123 static int enable_smbus(void)
128 /* Set the SMBus device statically. */
129 dev = PCI_BDF(0x0, 0x1f, 0x3);
131 /* Check to make sure we've got the right device. */
132 value = x86_pci_read_config16(dev, 0x0);
133 if (value != 0x8086) {
134 printf("SMBus controller not found\n");
138 /* Set SMBus I/O base. */
139 x86_pci_write_config32(dev, SMB_BASE,
140 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
142 /* Set SMBus enable. */
143 x86_pci_write_config8(dev, HOSTC, HST_EN);
145 /* Set SMBus I/O space enable. */
146 x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
148 /* Disable interrupt generation. */
149 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
151 /* Clear any lingering errors, so transactions can run. */
152 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
153 debug("SMBus controller enabled\n");
158 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
159 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
160 #define PCH_XHCI_TEMP_BAR0 0xe8001000
163 * Setup USB controller MMIO BAR to prevent the reference code from
164 * resetting the controller.
166 * The BAR will be re-assigned during device enumeration so these are only
169 * This is used to speed up the resume path.
171 static void enable_usb_bar(void)
173 pci_dev_t usb0 = PCH_EHCI1_DEV;
174 pci_dev_t usb1 = PCH_EHCI2_DEV;
175 pci_dev_t usb3 = PCH_XHCI_DEV;
178 /* USB Controller 1 */
179 x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
180 PCH_EHCI0_TEMP_BAR0);
181 cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
182 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
183 x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
185 /* USB Controller 1 */
186 x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
187 PCH_EHCI1_TEMP_BAR0);
188 cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
189 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
190 x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
192 /* USB3 Controller */
193 x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
195 cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
196 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
197 x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
200 static int report_bist_failure(void)
202 if (gd->arch.bist != 0) {
203 post_code(POST_BIST_FAILURE);
204 printf("BIST failed: %08x\n", gd->arch.bist);
211 int print_cpuinfo(void)
213 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
214 char processor_name[CPU_MAX_NAME_LEN];
221 /* Halt if there was a built in self test failure */
222 ret = report_bist_failure();
228 ret = microcode_update_intel();
232 /* Enable upper 128bytes of CMOS */
233 writel(1 << 2, RCB_REG(RC));
235 /* TODO: cmos_post_init() */
236 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
237 debug("soft reset detected\n");
238 boot_mode = PEI_BOOT_SOFT_RESET;
240 /* System is not happy after keyboard reset... */
241 debug("Issuing CF9 warm reset\n");
245 /* Early chipset init required before RAM init can work */
246 ret = uclass_first_device(UCLASS_PCH, &dev);
252 sandybridge_early_init(SANDYBRIDGE_MOBILE);
254 /* Check PM1_STS[15] to see if we are waking from Sx */
255 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
257 /* Read PM1_CNT[12:10] to determine which Sx state */
258 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
260 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
261 debug("Resume from S3 detected, but disabled.\n");
264 * TODO: An indication of life might be possible here (e.g.
268 post_code(POST_EARLY_INIT);
270 /* Enable SPD ROMs and DDR-III DRAM */
271 ret = enable_smbus();
275 /* Prepare USB controller early in S3 resume */
276 if (boot_mode == PEI_BOOT_RESUME)
279 gd->arch.pei_boot_mode = boot_mode;
281 /* TODO: Move this to the board or driver */
282 x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
283 x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
285 /* Print processor name */
286 name = cpu_get_name(processor_name);
287 printf("CPU: %s\n", name);
289 post_code(POST_CPU_INFO);
294 void board_debug_uart_init(void)
296 /* This enables the debug UART */
297 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,